RTOS 1.0
stm32f469xx.h
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33#ifndef __STM32F469xx_H
34#define __STM32F469xx_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif /* __cplusplus */
39
43
47#define __CM4_REV 0x0001U
48#define __MPU_PRESENT 1U
49#define __NVIC_PRIO_BITS 4U
50#define __Vendor_SysTickConfig 0U
51#define __FPU_PRESENT 1U
52
56
60
65typedef enum
66{
67 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
76 /****** STM32 specific Interrupt Numbers **********************************************************************/
95 ADC_IRQn = 18,
125 FMC_IRQn = 48,
138 ETH_IRQn = 61,
157 FPU_IRQn = 81,
169} IRQn_Type;
170
174
175#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
176#include "system_stm32f4xx.h"
177#include <stdint.h>
178
182
186
187typedef struct
188{
189 __IO uint32_t SR;
190 __IO uint32_t CR1;
191 __IO uint32_t CR2;
192 __IO uint32_t SMPR1;
193 __IO uint32_t SMPR2;
194 __IO uint32_t JOFR1;
195 __IO uint32_t JOFR2;
196 __IO uint32_t JOFR3;
197 __IO uint32_t JOFR4;
198 __IO uint32_t HTR;
199 __IO uint32_t LTR;
200 __IO uint32_t SQR1;
201 __IO uint32_t SQR2;
202 __IO uint32_t SQR3;
203 __IO uint32_t JSQR;
204 __IO uint32_t JDR1;
205 __IO uint32_t JDR2;
206 __IO uint32_t JDR3;
207 __IO uint32_t JDR4;
208 __IO uint32_t DR;
210
211typedef struct
212{
213 __IO uint32_t CSR;
214 __IO uint32_t CCR;
215 __IO uint32_t CDR;
218
219
223
224typedef struct
225{
226 __IO uint32_t TIR;
227 __IO uint32_t TDTR;
228 __IO uint32_t TDLR;
229 __IO uint32_t TDHR;
231
235
236typedef struct
237{
238 __IO uint32_t RIR;
239 __IO uint32_t RDTR;
240 __IO uint32_t RDLR;
241 __IO uint32_t RDHR;
243
247
248typedef struct
249{
250 __IO uint32_t FR1;
251 __IO uint32_t FR2;
253
257
258typedef struct
259{
260 __IO uint32_t MCR;
261 __IO uint32_t MSR;
262 __IO uint32_t TSR;
263 __IO uint32_t RF0R;
264 __IO uint32_t RF1R;
265 __IO uint32_t IER;
266 __IO uint32_t ESR;
267 __IO uint32_t BTR;
268 uint32_t RESERVED0[88];
269 CAN_TxMailBox_TypeDef sTxMailBox[3];
270 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
271 uint32_t RESERVED1[12];
272 __IO uint32_t FMR;
273 __IO uint32_t FM1R;
274 uint32_t RESERVED2;
275 __IO uint32_t FS1R;
276 uint32_t RESERVED3;
277 __IO uint32_t FFA1R;
278 uint32_t RESERVED4;
279 __IO uint32_t FA1R;
280 uint32_t RESERVED5[8];
281 CAN_FilterRegister_TypeDef sFilterRegister[28];
283
287
288typedef struct
289{
290 __IO uint32_t DR;
291 __IO uint8_t IDR;
292 uint8_t RESERVED0;
293 uint16_t RESERVED1;
294 __IO uint32_t CR;
296
300
301typedef struct
302{
303 __IO uint32_t CR;
304 __IO uint32_t SWTRIGR;
305 __IO uint32_t DHR12R1;
306 __IO uint32_t DHR12L1;
307 __IO uint32_t DHR8R1;
308 __IO uint32_t DHR12R2;
309 __IO uint32_t DHR12L2;
310 __IO uint32_t DHR8R2;
311 __IO uint32_t DHR12RD;
312 __IO uint32_t DHR12LD;
313 __IO uint32_t DHR8RD;
314 __IO uint32_t DOR1;
315 __IO uint32_t DOR2;
316 __IO uint32_t SR;
318
322
323typedef struct
324{
325 __IO uint32_t IDCODE;
326 __IO uint32_t CR;
327 __IO uint32_t APB1FZ;
328 __IO uint32_t APB2FZ;
330
334
335typedef struct
336{
337 __IO uint32_t CR;
338 __IO uint32_t SR;
339 __IO uint32_t RISR;
340 __IO uint32_t IER;
341 __IO uint32_t MISR;
342 __IO uint32_t ICR;
343 __IO uint32_t ESCR;
344 __IO uint32_t ESUR;
345 __IO uint32_t CWSTRTR;
346 __IO uint32_t CWSIZER;
347 __IO uint32_t DR;
349
353
354typedef struct
355{
356 __IO uint32_t CR;
357 __IO uint32_t NDTR;
358 __IO uint32_t PAR;
359 __IO uint32_t M0AR;
360 __IO uint32_t M1AR;
361 __IO uint32_t FCR;
363
364typedef struct
365{
366 __IO uint32_t LISR;
367 __IO uint32_t HISR;
368 __IO uint32_t LIFCR;
369 __IO uint32_t HIFCR;
371
375
376typedef struct
377{
378 __IO uint32_t CR;
379 __IO uint32_t ISR;
380 __IO uint32_t IFCR;
381 __IO uint32_t FGMAR;
382 __IO uint32_t FGOR;
383 __IO uint32_t BGMAR;
384 __IO uint32_t BGOR;
385 __IO uint32_t FGPFCCR;
386 __IO uint32_t FGCOLR;
387 __IO uint32_t BGPFCCR;
388 __IO uint32_t BGCOLR;
389 __IO uint32_t FGCMAR;
390 __IO uint32_t BGCMAR;
391 __IO uint32_t OPFCCR;
392 __IO uint32_t OCOLR;
393 __IO uint32_t OMAR;
394 __IO uint32_t OOR;
395 __IO uint32_t NLR;
396 __IO uint32_t LWR;
397 __IO uint32_t AMTCR;
398 uint32_t RESERVED[236];
399 __IO uint32_t FGCLUT[256];
400 __IO uint32_t BGCLUT[256];
402
406
407typedef struct
408{
409 __IO uint32_t VR;
410 __IO uint32_t CR;
411 __IO uint32_t CCR;
412 __IO uint32_t LVCIDR;
413 __IO uint32_t LCOLCR;
414 __IO uint32_t LPCR;
415 __IO uint32_t LPMCR;
416 uint32_t RESERVED0[4];
417 __IO uint32_t PCR;
418 __IO uint32_t GVCIDR;
419 __IO uint32_t MCR;
420 __IO uint32_t VMCR;
421 __IO uint32_t VPCR;
422 __IO uint32_t VCCR;
423 __IO uint32_t VNPCR;
424 __IO uint32_t VHSACR;
425 __IO uint32_t VHBPCR;
426 __IO uint32_t VLCR;
427 __IO uint32_t VVSACR;
428 __IO uint32_t VVBPCR;
429 __IO uint32_t VVFPCR;
430 __IO uint32_t VVACR;
431 __IO uint32_t LCCR;
432 __IO uint32_t CMCR;
433 __IO uint32_t GHCR;
434 __IO uint32_t GPDR;
435 __IO uint32_t GPSR;
436 __IO uint32_t TCCR[6];
437 __IO uint32_t TDCR;
438 __IO uint32_t CLCR;
439 __IO uint32_t CLTCR;
440 __IO uint32_t DLTCR;
441 __IO uint32_t PCTLR;
442 __IO uint32_t PCONFR;
443 __IO uint32_t PUCR;
444 __IO uint32_t PTTCR;
445 __IO uint32_t PSR;
446 uint32_t RESERVED1[2];
447 __IO uint32_t ISR[2];
448 __IO uint32_t IER[2];
449 uint32_t RESERVED2[3];
450 __IO uint32_t FIR[2];
451 uint32_t RESERVED3[8];
452 __IO uint32_t VSCR;
453 uint32_t RESERVED4[2];
454 __IO uint32_t LCVCIDR;
455 __IO uint32_t LCCCR;
456 uint32_t RESERVED5;
457 __IO uint32_t LPMCCR;
458 uint32_t RESERVED6[7];
459 __IO uint32_t VMCCR;
460 __IO uint32_t VPCCR;
461 __IO uint32_t VCCCR;
462 __IO uint32_t VNPCCR;
463 __IO uint32_t VHSACCR;
464 __IO uint32_t VHBPCCR;
465 __IO uint32_t VLCCR;
466 __IO uint32_t VVSACCR;
467 __IO uint32_t VVBPCCR;
468 __IO uint32_t VVFPCCR;
469 __IO uint32_t VVACCR;
470 uint32_t RESERVED7[11];
471 __IO uint32_t TDCCR;
472 uint32_t RESERVED8[155];
473 __IO uint32_t WCFGR;
474 __IO uint32_t WCR;
475 __IO uint32_t WIER;
476 __IO uint32_t WISR;
477 __IO uint32_t WIFCR;
478 uint32_t RESERVED9;
479 __IO uint32_t WPCR[5];
480 uint32_t RESERVED10;
481 __IO uint32_t WRPCR;
483
487
488typedef struct
489{
490 __IO uint32_t MACCR;
491 __IO uint32_t MACFFR;
492 __IO uint32_t MACHTHR;
493 __IO uint32_t MACHTLR;
494 __IO uint32_t MACMIIAR;
495 __IO uint32_t MACMIIDR;
496 __IO uint32_t MACFCR;
497 __IO uint32_t MACVLANTR; /* 8 */
498 uint32_t RESERVED0[2];
499 __IO uint32_t MACRWUFFR; /* 11 */
500 __IO uint32_t MACPMTCSR;
501 uint32_t RESERVED1;
502 __IO uint32_t MACDBGR;
503 __IO uint32_t MACSR; /* 15 */
504 __IO uint32_t MACIMR;
505 __IO uint32_t MACA0HR;
506 __IO uint32_t MACA0LR;
507 __IO uint32_t MACA1HR;
508 __IO uint32_t MACA1LR;
509 __IO uint32_t MACA2HR;
510 __IO uint32_t MACA2LR;
511 __IO uint32_t MACA3HR;
512 __IO uint32_t MACA3LR; /* 24 */
513 uint32_t RESERVED2[40];
514 __IO uint32_t MMCCR; /* 65 */
515 __IO uint32_t MMCRIR;
516 __IO uint32_t MMCTIR;
517 __IO uint32_t MMCRIMR;
518 __IO uint32_t MMCTIMR; /* 69 */
519 uint32_t RESERVED3[14];
520 __IO uint32_t MMCTGFSCCR; /* 84 */
521 __IO uint32_t MMCTGFMSCCR;
522 uint32_t RESERVED4[5];
523 __IO uint32_t MMCTGFCR;
524 uint32_t RESERVED5[10];
525 __IO uint32_t MMCRFCECR;
526 __IO uint32_t MMCRFAECR;
527 uint32_t RESERVED6[10];
528 __IO uint32_t MMCRGUFCR;
529 uint32_t RESERVED7[334];
530 __IO uint32_t PTPTSCR;
531 __IO uint32_t PTPSSIR;
532 __IO uint32_t PTPTSHR;
533 __IO uint32_t PTPTSLR;
534 __IO uint32_t PTPTSHUR;
535 __IO uint32_t PTPTSLUR;
536 __IO uint32_t PTPTSAR;
537 __IO uint32_t PTPTTHR;
538 __IO uint32_t PTPTTLR;
539 __IO uint32_t RESERVED8;
540 __IO uint32_t PTPTSSR;
541 uint32_t RESERVED9[565];
542 __IO uint32_t DMABMR;
543 __IO uint32_t DMATPDR;
544 __IO uint32_t DMARPDR;
545 __IO uint32_t DMARDLAR;
546 __IO uint32_t DMATDLAR;
547 __IO uint32_t DMASR;
548 __IO uint32_t DMAOMR;
549 __IO uint32_t DMAIER;
550 __IO uint32_t DMAMFBOCR;
551 __IO uint32_t DMARSWTR;
552 uint32_t RESERVED10[8];
553 __IO uint32_t DMACHTDR;
554 __IO uint32_t DMACHRDR;
555 __IO uint32_t DMACHTBAR;
556 __IO uint32_t DMACHRBAR;
558
562
563typedef struct
564{
565 __IO uint32_t IMR;
566 __IO uint32_t EMR;
567 __IO uint32_t RTSR;
568 __IO uint32_t FTSR;
569 __IO uint32_t SWIER;
570 __IO uint32_t PR;
572
576
577typedef struct
578{
579 __IO uint32_t ACR;
580 __IO uint32_t KEYR;
581 __IO uint32_t OPTKEYR;
582 __IO uint32_t SR;
583 __IO uint32_t CR;
584 __IO uint32_t OPTCR;
585 __IO uint32_t OPTCR1;
587
591
592typedef struct
593{
594 __IO uint32_t BTCR[8];
596
600
601typedef struct
602{
603 __IO uint32_t BWTR[7];
605
609
610typedef struct
611{
612 __IO uint32_t PCR;
613 __IO uint32_t SR;
614 __IO uint32_t PMEM;
615 __IO uint32_t PATT;
616 uint32_t RESERVED;
617 __IO uint32_t ECCR;
619
623
624typedef struct
625{
626 __IO uint32_t SDCR[2];
627 __IO uint32_t SDTR[2];
628 __IO uint32_t SDCMR;
629 __IO uint32_t SDRTR;
630 __IO uint32_t SDSR;
632
636
637typedef struct
638{
639 __IO uint32_t MODER;
640 __IO uint32_t OTYPER;
641 __IO uint32_t OSPEEDR;
642 __IO uint32_t PUPDR;
643 __IO uint32_t IDR;
644 __IO uint32_t ODR;
645 __IO uint32_t BSRR;
646 __IO uint32_t LCKR;
647 __IO uint32_t AFR[2];
649
653
654typedef struct
655{
656 __IO uint32_t MEMRMP;
657 __IO uint32_t PMC;
658 __IO uint32_t EXTICR[4];
659 uint32_t RESERVED[2];
660 __IO uint32_t CMPCR;
662
666
667typedef struct
668{
669 __IO uint32_t CR1;
670 __IO uint32_t CR2;
671 __IO uint32_t OAR1;
672 __IO uint32_t OAR2;
673 __IO uint32_t DR;
674 __IO uint32_t SR1;
675 __IO uint32_t SR2;
676 __IO uint32_t CCR;
677 __IO uint32_t TRISE;
678 __IO uint32_t FLTR;
680
684
685typedef struct
686{
687 __IO uint32_t KR;
688 __IO uint32_t PR;
689 __IO uint32_t RLR;
690 __IO uint32_t SR;
692
696
697typedef struct
698{
699 uint32_t RESERVED0[2];
700 __IO uint32_t SSCR;
701 __IO uint32_t BPCR;
702 __IO uint32_t AWCR;
703 __IO uint32_t TWCR;
704 __IO uint32_t GCR;
705 uint32_t RESERVED1[2];
706 __IO uint32_t SRCR;
707 uint32_t RESERVED2[1];
708 __IO uint32_t BCCR;
709 uint32_t RESERVED3[1];
710 __IO uint32_t IER;
711 __IO uint32_t ISR;
712 __IO uint32_t ICR;
713 __IO uint32_t LIPCR;
714 __IO uint32_t CPSR;
715 __IO uint32_t CDSR;
717
721
722typedef struct
723{
724 __IO uint32_t CR;
725 __IO uint32_t WHPCR;
726 __IO uint32_t WVPCR;
727 __IO uint32_t CKCR;
728 __IO uint32_t PFCR;
729 __IO uint32_t CACR;
730 __IO uint32_t DCCR;
731 __IO uint32_t BFCR;
732 uint32_t RESERVED0[2];
733 __IO uint32_t CFBAR;
734 __IO uint32_t CFBLR;
735 __IO uint32_t CFBLNR;
736 uint32_t RESERVED1[3];
737 __IO uint32_t CLUTWR;
739
743
744typedef struct
745{
746 __IO uint32_t CR;
747 __IO uint32_t CSR;
749
753
754typedef struct
755{
756 __IO uint32_t CR;
757 __IO uint32_t PLLCFGR;
758 __IO uint32_t CFGR;
759 __IO uint32_t CIR;
760 __IO uint32_t AHB1RSTR;
761 __IO uint32_t AHB2RSTR;
762 __IO uint32_t AHB3RSTR;
763 uint32_t RESERVED0;
764 __IO uint32_t APB1RSTR;
765 __IO uint32_t APB2RSTR;
766 uint32_t RESERVED1[2];
767 __IO uint32_t AHB1ENR;
768 __IO uint32_t AHB2ENR;
769 __IO uint32_t AHB3ENR;
770 uint32_t RESERVED2;
771 __IO uint32_t APB1ENR;
772 __IO uint32_t APB2ENR;
773 uint32_t RESERVED3[2];
774 __IO uint32_t AHB1LPENR;
775 __IO uint32_t AHB2LPENR;
776 __IO uint32_t AHB3LPENR;
777 uint32_t RESERVED4;
778 __IO uint32_t APB1LPENR;
779 __IO uint32_t APB2LPENR;
780 uint32_t RESERVED5[2];
781 __IO uint32_t BDCR;
782 __IO uint32_t CSR;
783 uint32_t RESERVED6[2];
784 __IO uint32_t SSCGR;
785 __IO uint32_t PLLI2SCFGR;
786 __IO uint32_t PLLSAICFGR;
787 __IO uint32_t DCKCFGR;
789
793
794typedef struct
795{
796 __IO uint32_t TR;
797 __IO uint32_t DR;
798 __IO uint32_t CR;
799 __IO uint32_t ISR;
800 __IO uint32_t PRER;
801 __IO uint32_t WUTR;
802 __IO uint32_t CALIBR;
803 __IO uint32_t ALRMAR;
804 __IO uint32_t ALRMBR;
805 __IO uint32_t WPR;
806 __IO uint32_t SSR;
807 __IO uint32_t SHIFTR;
808 __IO uint32_t TSTR;
809 __IO uint32_t TSDR;
810 __IO uint32_t TSSSR;
811 __IO uint32_t CALR;
812 __IO uint32_t TAFCR;
813 __IO uint32_t ALRMASSR;
814 __IO uint32_t ALRMBSSR;
815 uint32_t RESERVED7;
816 __IO uint32_t BKP0R;
817 __IO uint32_t BKP1R;
818 __IO uint32_t BKP2R;
819 __IO uint32_t BKP3R;
820 __IO uint32_t BKP4R;
821 __IO uint32_t BKP5R;
822 __IO uint32_t BKP6R;
823 __IO uint32_t BKP7R;
824 __IO uint32_t BKP8R;
825 __IO uint32_t BKP9R;
826 __IO uint32_t BKP10R;
827 __IO uint32_t BKP11R;
828 __IO uint32_t BKP12R;
829 __IO uint32_t BKP13R;
830 __IO uint32_t BKP14R;
831 __IO uint32_t BKP15R;
832 __IO uint32_t BKP16R;
833 __IO uint32_t BKP17R;
834 __IO uint32_t BKP18R;
835 __IO uint32_t BKP19R;
837
841
842typedef struct
843{
844 __IO uint32_t GCR;
846
847typedef struct
848{
849 __IO uint32_t CR1;
850 __IO uint32_t CR2;
851 __IO uint32_t FRCR;
852 __IO uint32_t SLOTR;
853 __IO uint32_t IMR;
854 __IO uint32_t SR;
855 __IO uint32_t CLRFR;
856 __IO uint32_t DR;
858
862
863typedef struct
864{
865 __IO uint32_t POWER;
866 __IO uint32_t CLKCR;
867 __IO uint32_t ARG;
868 __IO uint32_t CMD;
869 __IO const uint32_t RESPCMD;
870 __IO const uint32_t RESP1;
871 __IO const uint32_t RESP2;
872 __IO const uint32_t RESP3;
873 __IO const uint32_t RESP4;
874 __IO uint32_t DTIMER;
875 __IO uint32_t DLEN;
876 __IO uint32_t DCTRL;
877 __IO const uint32_t DCOUNT;
878 __IO const uint32_t STA;
879 __IO uint32_t ICR;
880 __IO uint32_t MASK;
881 uint32_t RESERVED0[2];
882 __IO const uint32_t FIFOCNT;
883 uint32_t RESERVED1[13];
884 __IO uint32_t FIFO;
886
890
891typedef struct
892{
893 __IO uint32_t CR1;
894 __IO uint32_t CR2;
895 __IO uint32_t SR;
896 __IO uint32_t DR;
897 __IO uint32_t CRCPR;
898 __IO uint32_t RXCRCR;
899 __IO uint32_t TXCRCR;
900 __IO uint32_t I2SCFGR;
901 __IO uint32_t I2SPR;
903
907
908typedef struct
909{
910 __IO uint32_t CR;
911 __IO uint32_t DCR;
912 __IO uint32_t SR;
913 __IO uint32_t FCR;
914 __IO uint32_t DLR;
915 __IO uint32_t CCR;
916 __IO uint32_t AR;
917 __IO uint32_t ABR;
918 __IO uint32_t DR;
919 __IO uint32_t PSMKR;
920 __IO uint32_t PSMAR;
921 __IO uint32_t PIR;
922 __IO uint32_t LPTR;
924
928
929typedef struct
930{
931 __IO uint32_t CR1;
932 __IO uint32_t CR2;
933 __IO uint32_t SMCR;
934 __IO uint32_t DIER;
935 __IO uint32_t SR;
936 __IO uint32_t EGR;
937 __IO uint32_t CCMR1;
938 __IO uint32_t CCMR2;
939 __IO uint32_t CCER;
940 __IO uint32_t CNT;
941 __IO uint32_t PSC;
942 __IO uint32_t ARR;
943 __IO uint32_t RCR;
944 __IO uint32_t CCR1;
945 __IO uint32_t CCR2;
946 __IO uint32_t CCR3;
947 __IO uint32_t CCR4;
948 __IO uint32_t BDTR;
949 __IO uint32_t DCR;
950 __IO uint32_t DMAR;
951 __IO uint32_t OR;
953
957
958typedef struct
959{
960 __IO uint32_t SR;
961 __IO uint32_t DR;
962 __IO uint32_t BRR;
963 __IO uint32_t CR1;
964 __IO uint32_t CR2;
965 __IO uint32_t CR3;
966 __IO uint32_t GTPR;
968
972
973typedef struct
974{
975 __IO uint32_t CR;
976 __IO uint32_t CFR;
977 __IO uint32_t SR;
979
983
984typedef struct
985{
986 __IO uint32_t CR;
987 __IO uint32_t SR;
988 __IO uint32_t DR;
990
994typedef struct
995{
996 __IO uint32_t GOTGCTL;
997 __IO uint32_t GOTGINT;
998 __IO uint32_t GAHBCFG;
999 __IO uint32_t GUSBCFG;
1000 __IO uint32_t GRSTCTL;
1001 __IO uint32_t GINTSTS;
1002 __IO uint32_t GINTMSK;
1003 __IO uint32_t GRXSTSR;
1004 __IO uint32_t GRXSTSP;
1005 __IO uint32_t GRXFSIZ;
1006 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1007 __IO uint32_t HNPTXSTS;
1008 uint32_t Reserved30[2];
1009 __IO uint32_t GCCFG;
1010 __IO uint32_t CID;
1011 uint32_t Reserved5[3];
1012 __IO uint32_t GHWCFG3;
1013 uint32_t Reserved6;
1014 __IO uint32_t GLPMCFG;
1015 uint32_t Reserved;
1016 __IO uint32_t GDFIFOCFG;
1017 uint32_t Reserved43[40];
1018 __IO uint32_t HPTXFSIZ;
1019 __IO uint32_t DIEPTXF[0x0F];
1021
1025typedef struct
1026{
1027 __IO uint32_t DCFG;
1028 __IO uint32_t DCTL;
1029 __IO uint32_t DSTS;
1030 uint32_t Reserved0C;
1031 __IO uint32_t DIEPMSK;
1032 __IO uint32_t DOEPMSK;
1033 __IO uint32_t DAINT;
1034 __IO uint32_t DAINTMSK;
1035 uint32_t Reserved20;
1036 uint32_t Reserved9;
1037 __IO uint32_t DVBUSDIS;
1038 __IO uint32_t DVBUSPULSE;
1039 __IO uint32_t DTHRCTL;
1040 __IO uint32_t DIEPEMPMSK;
1041 __IO uint32_t DEACHINT;
1042 __IO uint32_t DEACHMSK;
1043 uint32_t Reserved40;
1044 __IO uint32_t DINEP1MSK;
1045 uint32_t Reserved44[15];
1046 __IO uint32_t DOUTEP1MSK;
1048
1052typedef struct
1053{
1054 __IO uint32_t DIEPCTL;
1055 uint32_t Reserved04;
1056 __IO uint32_t DIEPINT;
1057 uint32_t Reserved0C;
1058 __IO uint32_t DIEPTSIZ;
1059 __IO uint32_t DIEPDMA;
1060 __IO uint32_t DTXFSTS;
1061 uint32_t Reserved18;
1063
1067typedef struct
1068{
1069 __IO uint32_t DOEPCTL;
1070 uint32_t Reserved04;
1071 __IO uint32_t DOEPINT;
1072 uint32_t Reserved0C;
1073 __IO uint32_t DOEPTSIZ;
1074 __IO uint32_t DOEPDMA;
1075 uint32_t Reserved18[2];
1077
1081typedef struct
1082{
1083 __IO uint32_t HCFG;
1084 __IO uint32_t HFIR;
1085 __IO uint32_t HFNUM;
1086 uint32_t Reserved40C;
1087 __IO uint32_t HPTXSTS;
1088 __IO uint32_t HAINT;
1089 __IO uint32_t HAINTMSK;
1091
1095typedef struct
1096{
1097 __IO uint32_t HCCHAR;
1098 __IO uint32_t HCSPLT;
1099 __IO uint32_t HCINT;
1100 __IO uint32_t HCINTMSK;
1101 __IO uint32_t HCTSIZ;
1102 __IO uint32_t HCDMA;
1103 uint32_t Reserved[2];
1105
1109
1113#define FLASH_BASE 0x08000000UL
1114#define CCMDATARAM_BASE 0x10000000UL
1115#define SRAM1_BASE 0x20000000UL
1116#define SRAM2_BASE 0x20028000UL
1117#define SRAM3_BASE 0x20030000UL
1118#define PERIPH_BASE 0x40000000UL
1119#define BKPSRAM_BASE 0x40024000UL
1120#define FMC_R_BASE 0xA0000000UL
1121#define QSPI_R_BASE 0xA0001000UL
1122#define SRAM1_BB_BASE 0x22000000UL
1123#define SRAM2_BB_BASE 0x22500000UL
1124#define SRAM3_BB_BASE 0x22600000UL
1125#define PERIPH_BB_BASE 0x42000000UL
1126#define BKPSRAM_BB_BASE 0x42480000UL
1127#define FLASH_END 0x081FFFFFUL
1128#define FLASH_OTP_BASE 0x1FFF7800UL
1129#define FLASH_OTP_END 0x1FFF7A0FUL
1130#define CCMDATARAM_END 0x1000FFFFUL
1131
1132/* Legacy defines */
1133#define SRAM_BASE SRAM1_BASE
1134#define SRAM_BB_BASE SRAM1_BB_BASE
1135
1137#define APB1PERIPH_BASE PERIPH_BASE
1138#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1139#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1140#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1141
1143#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
1144#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
1145#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
1146#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
1147#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
1148#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
1149#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
1150#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
1151#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
1152#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
1153#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
1154#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
1155#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
1156#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
1157#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
1158#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
1159#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
1160#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
1161#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
1162#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
1163#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
1164#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
1165#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
1166#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
1167#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
1168#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
1169#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
1170#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
1171#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
1172
1174#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
1175#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
1176#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
1177#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
1178#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
1179#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
1180#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
1181#define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
1182/* Legacy define */
1183#define ADC_BASE ADC123_COMMON_BASE
1184#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
1185#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
1186#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
1187#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
1188#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
1189#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
1190#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
1191#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
1192#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
1193#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL)
1194#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
1195#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
1196#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
1197#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL)
1198#define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1199#define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1200#define DSI_BASE (APB2PERIPH_BASE + 0x6C00UL)
1201
1203#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
1204#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1205#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1206#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1207#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1208#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1209#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1210#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1211#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1212#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL)
1213#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL)
1214#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1215#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1216#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1217#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1218#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1219#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1220#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1221#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1222#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1223#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1224#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1225#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1226#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1227#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1228#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1229#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1230#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1231#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1232#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1233#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1234#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1235#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL)
1236#define ETH_MAC_BASE (ETH_BASE)
1237#define ETH_MMC_BASE (ETH_BASE + 0x0100UL)
1238#define ETH_PTP_BASE (ETH_BASE + 0x0700UL)
1239#define ETH_DMA_BASE (ETH_BASE + 0x1000UL)
1240#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL)
1241
1243#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL)
1244#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1245
1247#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1248#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1249#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1250#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1251
1252
1254#define DBGMCU_BASE 0xE0042000UL
1256#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1257#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1258
1259#define USB_OTG_GLOBAL_BASE 0x000UL
1260#define USB_OTG_DEVICE_BASE 0x800UL
1261#define USB_OTG_IN_ENDPOINT_BASE 0x900UL
1262#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
1263#define USB_OTG_EP_REG_SIZE 0x20UL
1264#define USB_OTG_HOST_BASE 0x400UL
1265#define USB_OTG_HOST_PORT_BASE 0x440UL
1266#define USB_OTG_HOST_CHANNEL_BASE 0x500UL
1267#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
1268#define USB_OTG_PCGCCTL_BASE 0xE00UL
1269#define USB_OTG_FIFO_BASE 0x1000UL
1270#define USB_OTG_FIFO_SIZE 0x1000UL
1271
1272#define UID_BASE 0x1FFF7A10UL
1273#define FLASHSIZE_BASE 0x1FFF7A22UL
1274#define PACKAGE_BASE 0x1FFF7BF0UL
1278
1282#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1283#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1284#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1285#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1286#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1287#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1288#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1289#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1290#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1291#define RTC ((RTC_TypeDef *) RTC_BASE)
1292#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1293#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1294#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1295#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1296#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1297#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1298#define USART2 ((USART_TypeDef *) USART2_BASE)
1299#define USART3 ((USART_TypeDef *) USART3_BASE)
1300#define UART4 ((USART_TypeDef *) UART4_BASE)
1301#define UART5 ((USART_TypeDef *) UART5_BASE)
1302#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1303#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1304#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1305#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1306#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1307#define PWR ((PWR_TypeDef *) PWR_BASE)
1308#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1309#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1310#define UART7 ((USART_TypeDef *) UART7_BASE)
1311#define UART8 ((USART_TypeDef *) UART8_BASE)
1312#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1313#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1314#define USART1 ((USART_TypeDef *) USART1_BASE)
1315#define USART6 ((USART_TypeDef *) USART6_BASE)
1316#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1317#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1318#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1319#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1320/* Legacy define */
1321#define ADC ADC123_COMMON
1322#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1323#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1324#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1325#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1326#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1327#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1328#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1329#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1330#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1331#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1332#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1333#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1334#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1335#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1336#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1337#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1338#define DSI ((DSI_TypeDef *)DSI_BASE)
1339#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1340#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1341#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1342#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1343#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1344#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1345#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1346#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1347#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1348#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1349#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1350#define CRC ((CRC_TypeDef *) CRC_BASE)
1351#define RCC ((RCC_TypeDef *) RCC_BASE)
1352#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1353#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1354#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1355#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1356#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1357#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1358#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1359#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1360#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1361#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1362#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1363#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1364#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1365#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1366#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1367#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1368#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1369#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1370#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1371#define ETH ((ETH_TypeDef *) ETH_BASE)
1372#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1373#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1374#define RNG ((RNG_TypeDef *) RNG_BASE)
1375#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1376#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1377#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1378#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1379#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1380#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1381#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1382#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1383
1387
1391
1395#define LSI_STARTUP_TIME 40U
1399
1403
1404/******************************************************************************/
1405/* Peripheral Registers_Bits_Definition */
1406/******************************************************************************/
1407
1408/******************************************************************************/
1409/* */
1410/* Analog to Digital Converter */
1411/* */
1412/******************************************************************************/
1413/*
1414 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
1415 */
1416#define ADC_MULTIMODE_SUPPORT
1417
1418/******************** Bit definition for ADC_SR register ********************/
1419#define ADC_SR_AWD_Pos (0U)
1420#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1421#define ADC_SR_AWD ADC_SR_AWD_Msk
1422#define ADC_SR_EOC_Pos (1U)
1423#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1424#define ADC_SR_EOC ADC_SR_EOC_Msk
1425#define ADC_SR_JEOC_Pos (2U)
1426#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1427#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1428#define ADC_SR_JSTRT_Pos (3U)
1429#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1430#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1431#define ADC_SR_STRT_Pos (4U)
1432#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1433#define ADC_SR_STRT ADC_SR_STRT_Msk
1434#define ADC_SR_OVR_Pos (5U)
1435#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1436#define ADC_SR_OVR ADC_SR_OVR_Msk
1437
1438/******************* Bit definition for ADC_CR1 register ********************/
1439#define ADC_CR1_AWDCH_Pos (0U)
1440#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1441#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1442#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1443#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1444#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1445#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1446#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1447#define ADC_CR1_EOCIE_Pos (5U)
1448#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1449#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1450#define ADC_CR1_AWDIE_Pos (6U)
1451#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1452#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1453#define ADC_CR1_JEOCIE_Pos (7U)
1454#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1455#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1456#define ADC_CR1_SCAN_Pos (8U)
1457#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1458#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1459#define ADC_CR1_AWDSGL_Pos (9U)
1460#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1461#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1462#define ADC_CR1_JAUTO_Pos (10U)
1463#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1464#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1465#define ADC_CR1_DISCEN_Pos (11U)
1466#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1467#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1468#define ADC_CR1_JDISCEN_Pos (12U)
1469#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1470#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1471#define ADC_CR1_DISCNUM_Pos (13U)
1472#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1473#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1474#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1475#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1476#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1477#define ADC_CR1_JAWDEN_Pos (22U)
1478#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1479#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1480#define ADC_CR1_AWDEN_Pos (23U)
1481#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1482#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1483#define ADC_CR1_RES_Pos (24U)
1484#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1485#define ADC_CR1_RES ADC_CR1_RES_Msk
1486#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1487#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1488#define ADC_CR1_OVRIE_Pos (26U)
1489#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1490#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1491
1492/******************* Bit definition for ADC_CR2 register ********************/
1493#define ADC_CR2_ADON_Pos (0U)
1494#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1495#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1496#define ADC_CR2_CONT_Pos (1U)
1497#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1498#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1499#define ADC_CR2_DMA_Pos (8U)
1500#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1501#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1502#define ADC_CR2_DDS_Pos (9U)
1503#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1504#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1505#define ADC_CR2_EOCS_Pos (10U)
1506#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1507#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1508#define ADC_CR2_ALIGN_Pos (11U)
1509#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1510#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1511#define ADC_CR2_JEXTSEL_Pos (16U)
1512#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1513#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1514#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1515#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1516#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1517#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1518#define ADC_CR2_JEXTEN_Pos (20U)
1519#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1520#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1521#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1522#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1523#define ADC_CR2_JSWSTART_Pos (22U)
1524#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1525#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1526#define ADC_CR2_EXTSEL_Pos (24U)
1527#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1528#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1529#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1530#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1531#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1532#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1533#define ADC_CR2_EXTEN_Pos (28U)
1534#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1535#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1536#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1537#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1538#define ADC_CR2_SWSTART_Pos (30U)
1539#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1540#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1541
1542/****************** Bit definition for ADC_SMPR1 register *******************/
1543#define ADC_SMPR1_SMP10_Pos (0U)
1544#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1545#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1546#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1547#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1548#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1549#define ADC_SMPR1_SMP11_Pos (3U)
1550#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1551#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1552#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1553#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1554#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1555#define ADC_SMPR1_SMP12_Pos (6U)
1556#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1557#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1558#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1559#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1560#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1561#define ADC_SMPR1_SMP13_Pos (9U)
1562#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1563#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1564#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1565#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1566#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1567#define ADC_SMPR1_SMP14_Pos (12U)
1568#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1569#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1570#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1571#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1572#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1573#define ADC_SMPR1_SMP15_Pos (15U)
1574#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1575#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1576#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1577#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1578#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1579#define ADC_SMPR1_SMP16_Pos (18U)
1580#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1581#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1582#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1583#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1584#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1585#define ADC_SMPR1_SMP17_Pos (21U)
1586#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1587#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1588#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1589#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1590#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1591#define ADC_SMPR1_SMP18_Pos (24U)
1592#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1593#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1594#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1595#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1596#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1597
1598/****************** Bit definition for ADC_SMPR2 register *******************/
1599#define ADC_SMPR2_SMP0_Pos (0U)
1600#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1601#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1602#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1603#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1604#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1605#define ADC_SMPR2_SMP1_Pos (3U)
1606#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1607#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1608#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1609#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1610#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1611#define ADC_SMPR2_SMP2_Pos (6U)
1612#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1613#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1614#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1615#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1616#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1617#define ADC_SMPR2_SMP3_Pos (9U)
1618#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1619#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1620#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1621#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1622#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1623#define ADC_SMPR2_SMP4_Pos (12U)
1624#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1625#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1626#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1627#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1628#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1629#define ADC_SMPR2_SMP5_Pos (15U)
1630#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1631#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1632#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1633#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1634#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1635#define ADC_SMPR2_SMP6_Pos (18U)
1636#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1637#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1638#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1639#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1640#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1641#define ADC_SMPR2_SMP7_Pos (21U)
1642#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1643#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1644#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1645#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1646#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1647#define ADC_SMPR2_SMP8_Pos (24U)
1648#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1649#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1650#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1651#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1652#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1653#define ADC_SMPR2_SMP9_Pos (27U)
1654#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1655#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1656#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1657#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1658#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1659
1660/****************** Bit definition for ADC_JOFR1 register *******************/
1661#define ADC_JOFR1_JOFFSET1_Pos (0U)
1662#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1663#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1664
1665/****************** Bit definition for ADC_JOFR2 register *******************/
1666#define ADC_JOFR2_JOFFSET2_Pos (0U)
1667#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1668#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1669
1670/****************** Bit definition for ADC_JOFR3 register *******************/
1671#define ADC_JOFR3_JOFFSET3_Pos (0U)
1672#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1673#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1674
1675/****************** Bit definition for ADC_JOFR4 register *******************/
1676#define ADC_JOFR4_JOFFSET4_Pos (0U)
1677#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1678#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1679
1680/******************* Bit definition for ADC_HTR register ********************/
1681#define ADC_HTR_HT_Pos (0U)
1682#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1683#define ADC_HTR_HT ADC_HTR_HT_Msk
1684
1685/******************* Bit definition for ADC_LTR register ********************/
1686#define ADC_LTR_LT_Pos (0U)
1687#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1688#define ADC_LTR_LT ADC_LTR_LT_Msk
1689
1690/******************* Bit definition for ADC_SQR1 register *******************/
1691#define ADC_SQR1_SQ13_Pos (0U)
1692#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1693#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1694#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1695#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1696#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1697#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1698#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1699#define ADC_SQR1_SQ14_Pos (5U)
1700#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1701#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1702#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1703#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1704#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1705#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1706#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1707#define ADC_SQR1_SQ15_Pos (10U)
1708#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1709#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1710#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1711#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1712#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1713#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1714#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1715#define ADC_SQR1_SQ16_Pos (15U)
1716#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1717#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1718#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1719#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1720#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1721#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1722#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1723#define ADC_SQR1_L_Pos (20U)
1724#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1725#define ADC_SQR1_L ADC_SQR1_L_Msk
1726#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1727#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1728#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1729#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1730
1731/******************* Bit definition for ADC_SQR2 register *******************/
1732#define ADC_SQR2_SQ7_Pos (0U)
1733#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1734#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1735#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1736#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1737#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1738#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1739#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1740#define ADC_SQR2_SQ8_Pos (5U)
1741#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1742#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1743#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1744#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1745#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1746#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1747#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1748#define ADC_SQR2_SQ9_Pos (10U)
1749#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1750#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1751#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1752#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1753#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1754#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1755#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1756#define ADC_SQR2_SQ10_Pos (15U)
1757#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1758#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1759#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1760#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1761#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1762#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1763#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1764#define ADC_SQR2_SQ11_Pos (20U)
1765#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1766#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1767#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1768#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1769#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1770#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1771#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1772#define ADC_SQR2_SQ12_Pos (25U)
1773#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1774#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1775#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1776#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1777#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1778#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1779#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1780
1781/******************* Bit definition for ADC_SQR3 register *******************/
1782#define ADC_SQR3_SQ1_Pos (0U)
1783#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1784#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1785#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1786#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1787#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1788#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1789#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1790#define ADC_SQR3_SQ2_Pos (5U)
1791#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1792#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1793#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1794#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1795#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1796#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1797#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1798#define ADC_SQR3_SQ3_Pos (10U)
1799#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1800#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1801#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1802#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1803#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1804#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1805#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1806#define ADC_SQR3_SQ4_Pos (15U)
1807#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1808#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1809#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1810#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1811#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1812#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1813#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1814#define ADC_SQR3_SQ5_Pos (20U)
1815#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1816#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1817#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1818#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1819#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1820#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1821#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1822#define ADC_SQR3_SQ6_Pos (25U)
1823#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1824#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1825#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1826#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1827#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1828#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1829#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1830
1831/******************* Bit definition for ADC_JSQR register *******************/
1832#define ADC_JSQR_JSQ1_Pos (0U)
1833#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1834#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1835#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1836#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1837#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1838#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1839#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1840#define ADC_JSQR_JSQ2_Pos (5U)
1841#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1842#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1843#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1844#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1845#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1846#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1847#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1848#define ADC_JSQR_JSQ3_Pos (10U)
1849#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1850#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1851#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1852#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1853#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1854#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1855#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1856#define ADC_JSQR_JSQ4_Pos (15U)
1857#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1858#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1859#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1860#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1861#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1862#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1863#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1864#define ADC_JSQR_JL_Pos (20U)
1865#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1866#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1867#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1868#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1869
1870/******************* Bit definition for ADC_JDR1 register *******************/
1871#define ADC_JDR1_JDATA_Pos (0U)
1872#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1873#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1874
1875/******************* Bit definition for ADC_JDR2 register *******************/
1876#define ADC_JDR2_JDATA_Pos (0U)
1877#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1878#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1879
1880/******************* Bit definition for ADC_JDR3 register *******************/
1881#define ADC_JDR3_JDATA_Pos (0U)
1882#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1883#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1884
1885/******************* Bit definition for ADC_JDR4 register *******************/
1886#define ADC_JDR4_JDATA_Pos (0U)
1887#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1888#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1889
1890/******************** Bit definition for ADC_DR register ********************/
1891#define ADC_DR_DATA_Pos (0U)
1892#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1893#define ADC_DR_DATA ADC_DR_DATA_Msk
1894#define ADC_DR_ADC2DATA_Pos (16U)
1895#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1896#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1897
1898/******************* Bit definition for ADC_CSR register ********************/
1899#define ADC_CSR_AWD1_Pos (0U)
1900#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1901#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1902#define ADC_CSR_EOC1_Pos (1U)
1903#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1904#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1905#define ADC_CSR_JEOC1_Pos (2U)
1906#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1907#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1908#define ADC_CSR_JSTRT1_Pos (3U)
1909#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1910#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1911#define ADC_CSR_STRT1_Pos (4U)
1912#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1913#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1914#define ADC_CSR_OVR1_Pos (5U)
1915#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1916#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1917#define ADC_CSR_AWD2_Pos (8U)
1918#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1919#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1920#define ADC_CSR_EOC2_Pos (9U)
1921#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1922#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1923#define ADC_CSR_JEOC2_Pos (10U)
1924#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1925#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1926#define ADC_CSR_JSTRT2_Pos (11U)
1927#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1928#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1929#define ADC_CSR_STRT2_Pos (12U)
1930#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1931#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1932#define ADC_CSR_OVR2_Pos (13U)
1933#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1934#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1935#define ADC_CSR_AWD3_Pos (16U)
1936#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1937#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1938#define ADC_CSR_EOC3_Pos (17U)
1939#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1940#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1941#define ADC_CSR_JEOC3_Pos (18U)
1942#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1943#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1944#define ADC_CSR_JSTRT3_Pos (19U)
1945#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1946#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1947#define ADC_CSR_STRT3_Pos (20U)
1948#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1949#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1950#define ADC_CSR_OVR3_Pos (21U)
1951#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1952#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1953
1954/* Legacy defines */
1955#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1956#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1957#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1958
1959/******************* Bit definition for ADC_CCR register ********************/
1960#define ADC_CCR_MULTI_Pos (0U)
1961#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1962#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1963#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1964#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1965#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1966#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1967#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1968#define ADC_CCR_DELAY_Pos (8U)
1969#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1970#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1971#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1972#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1973#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1974#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1975#define ADC_CCR_DDS_Pos (13U)
1976#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1977#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1978#define ADC_CCR_DMA_Pos (14U)
1979#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1980#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1981#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1982#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1983#define ADC_CCR_ADCPRE_Pos (16U)
1984#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1985#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1986#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1987#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1988#define ADC_CCR_VBATE_Pos (22U)
1989#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1990#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1991#define ADC_CCR_TSVREFE_Pos (23U)
1992#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1993#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1994
1995/******************* Bit definition for ADC_CDR register ********************/
1996#define ADC_CDR_DATA1_Pos (0U)
1997#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1998#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1999#define ADC_CDR_DATA2_Pos (16U)
2000#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
2001#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
2002
2003/* Legacy defines */
2004#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2005#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2006
2007/******************************************************************************/
2008/* */
2009/* Controller Area Network */
2010/* */
2011/******************************************************************************/
2013/******************* Bit definition for CAN_MCR register ********************/
2014#define CAN_MCR_INRQ_Pos (0U)
2015#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
2016#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
2017#define CAN_MCR_SLEEP_Pos (1U)
2018#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
2019#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
2020#define CAN_MCR_TXFP_Pos (2U)
2021#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
2022#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
2023#define CAN_MCR_RFLM_Pos (3U)
2024#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
2025#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
2026#define CAN_MCR_NART_Pos (4U)
2027#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
2028#define CAN_MCR_NART CAN_MCR_NART_Msk
2029#define CAN_MCR_AWUM_Pos (5U)
2030#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
2031#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
2032#define CAN_MCR_ABOM_Pos (6U)
2033#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
2034#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
2035#define CAN_MCR_TTCM_Pos (7U)
2036#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
2037#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
2038#define CAN_MCR_RESET_Pos (15U)
2039#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
2040#define CAN_MCR_RESET CAN_MCR_RESET_Msk
2041#define CAN_MCR_DBF_Pos (16U)
2042#define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
2043#define CAN_MCR_DBF CAN_MCR_DBF_Msk
2044/******************* Bit definition for CAN_MSR register ********************/
2045#define CAN_MSR_INAK_Pos (0U)
2046#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
2047#define CAN_MSR_INAK CAN_MSR_INAK_Msk
2048#define CAN_MSR_SLAK_Pos (1U)
2049#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
2050#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
2051#define CAN_MSR_ERRI_Pos (2U)
2052#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
2053#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
2054#define CAN_MSR_WKUI_Pos (3U)
2055#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
2056#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
2057#define CAN_MSR_SLAKI_Pos (4U)
2058#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
2059#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
2060#define CAN_MSR_TXM_Pos (8U)
2061#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
2062#define CAN_MSR_TXM CAN_MSR_TXM_Msk
2063#define CAN_MSR_RXM_Pos (9U)
2064#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
2065#define CAN_MSR_RXM CAN_MSR_RXM_Msk
2066#define CAN_MSR_SAMP_Pos (10U)
2067#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
2068#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
2069#define CAN_MSR_RX_Pos (11U)
2070#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
2071#define CAN_MSR_RX CAN_MSR_RX_Msk
2072
2073/******************* Bit definition for CAN_TSR register ********************/
2074#define CAN_TSR_RQCP0_Pos (0U)
2075#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
2076#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
2077#define CAN_TSR_TXOK0_Pos (1U)
2078#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
2079#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
2080#define CAN_TSR_ALST0_Pos (2U)
2081#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
2082#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
2083#define CAN_TSR_TERR0_Pos (3U)
2084#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
2085#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
2086#define CAN_TSR_ABRQ0_Pos (7U)
2087#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
2088#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
2089#define CAN_TSR_RQCP1_Pos (8U)
2090#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
2091#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
2092#define CAN_TSR_TXOK1_Pos (9U)
2093#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
2094#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
2095#define CAN_TSR_ALST1_Pos (10U)
2096#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
2097#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
2098#define CAN_TSR_TERR1_Pos (11U)
2099#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
2100#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
2101#define CAN_TSR_ABRQ1_Pos (15U)
2102#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
2103#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
2104#define CAN_TSR_RQCP2_Pos (16U)
2105#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
2106#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
2107#define CAN_TSR_TXOK2_Pos (17U)
2108#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
2109#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
2110#define CAN_TSR_ALST2_Pos (18U)
2111#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
2112#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
2113#define CAN_TSR_TERR2_Pos (19U)
2114#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
2115#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
2116#define CAN_TSR_ABRQ2_Pos (23U)
2117#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
2118#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
2119#define CAN_TSR_CODE_Pos (24U)
2120#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
2121#define CAN_TSR_CODE CAN_TSR_CODE_Msk
2122
2123#define CAN_TSR_TME_Pos (26U)
2124#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
2125#define CAN_TSR_TME CAN_TSR_TME_Msk
2126#define CAN_TSR_TME0_Pos (26U)
2127#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
2128#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
2129#define CAN_TSR_TME1_Pos (27U)
2130#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
2131#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
2132#define CAN_TSR_TME2_Pos (28U)
2133#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
2134#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
2135
2136#define CAN_TSR_LOW_Pos (29U)
2137#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
2138#define CAN_TSR_LOW CAN_TSR_LOW_Msk
2139#define CAN_TSR_LOW0_Pos (29U)
2140#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
2141#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
2142#define CAN_TSR_LOW1_Pos (30U)
2143#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
2144#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
2145#define CAN_TSR_LOW2_Pos (31U)
2146#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
2147#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
2148
2149/******************* Bit definition for CAN_RF0R register *******************/
2150#define CAN_RF0R_FMP0_Pos (0U)
2151#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
2152#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
2153#define CAN_RF0R_FULL0_Pos (3U)
2154#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
2155#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
2156#define CAN_RF0R_FOVR0_Pos (4U)
2157#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
2158#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
2159#define CAN_RF0R_RFOM0_Pos (5U)
2160#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
2161#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
2162
2163/******************* Bit definition for CAN_RF1R register *******************/
2164#define CAN_RF1R_FMP1_Pos (0U)
2165#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
2166#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
2167#define CAN_RF1R_FULL1_Pos (3U)
2168#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
2169#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
2170#define CAN_RF1R_FOVR1_Pos (4U)
2171#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
2172#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
2173#define CAN_RF1R_RFOM1_Pos (5U)
2174#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
2175#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
2176
2177/******************** Bit definition for CAN_IER register *******************/
2178#define CAN_IER_TMEIE_Pos (0U)
2179#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
2180#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
2181#define CAN_IER_FMPIE0_Pos (1U)
2182#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
2183#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
2184#define CAN_IER_FFIE0_Pos (2U)
2185#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
2186#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
2187#define CAN_IER_FOVIE0_Pos (3U)
2188#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
2189#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
2190#define CAN_IER_FMPIE1_Pos (4U)
2191#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
2192#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
2193#define CAN_IER_FFIE1_Pos (5U)
2194#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
2195#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
2196#define CAN_IER_FOVIE1_Pos (6U)
2197#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
2198#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
2199#define CAN_IER_EWGIE_Pos (8U)
2200#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
2201#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
2202#define CAN_IER_EPVIE_Pos (9U)
2203#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
2204#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
2205#define CAN_IER_BOFIE_Pos (10U)
2206#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
2207#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
2208#define CAN_IER_LECIE_Pos (11U)
2209#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
2210#define CAN_IER_LECIE CAN_IER_LECIE_Msk
2211#define CAN_IER_ERRIE_Pos (15U)
2212#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
2213#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
2214#define CAN_IER_WKUIE_Pos (16U)
2215#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
2216#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
2217#define CAN_IER_SLKIE_Pos (17U)
2218#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
2219#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
2220#define CAN_IER_EWGIE_Pos (8U)
2221
2222/******************** Bit definition for CAN_ESR register *******************/
2223#define CAN_ESR_EWGF_Pos (0U)
2224#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
2225#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
2226#define CAN_ESR_EPVF_Pos (1U)
2227#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
2228#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
2229#define CAN_ESR_BOFF_Pos (2U)
2230#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
2231#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
2232
2233#define CAN_ESR_LEC_Pos (4U)
2234#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
2235#define CAN_ESR_LEC CAN_ESR_LEC_Msk
2236#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
2237#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
2238#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
2239
2240#define CAN_ESR_TEC_Pos (16U)
2241#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2242#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2243#define CAN_ESR_REC_Pos (24U)
2244#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2245#define CAN_ESR_REC CAN_ESR_REC_Msk
2246
2247/******************* Bit definition for CAN_BTR register ********************/
2248#define CAN_BTR_BRP_Pos (0U)
2249#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2250#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2251#define CAN_BTR_TS1_Pos (16U)
2252#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2253#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2254#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2255#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2256#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2257#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2258#define CAN_BTR_TS2_Pos (20U)
2259#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2260#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2261#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2262#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2263#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2264#define CAN_BTR_SJW_Pos (24U)
2265#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2266#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2267#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2268#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2269#define CAN_BTR_LBKM_Pos (30U)
2270#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2271#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2272#define CAN_BTR_SILM_Pos (31U)
2273#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2274#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2275
2276
2278/****************** Bit definition for CAN_TI0R register ********************/
2279#define CAN_TI0R_TXRQ_Pos (0U)
2280#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2281#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2282#define CAN_TI0R_RTR_Pos (1U)
2283#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2284#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2285#define CAN_TI0R_IDE_Pos (2U)
2286#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2287#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2288#define CAN_TI0R_EXID_Pos (3U)
2289#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2290#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2291#define CAN_TI0R_STID_Pos (21U)
2292#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2293#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2294
2295/****************** Bit definition for CAN_TDT0R register *******************/
2296#define CAN_TDT0R_DLC_Pos (0U)
2297#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2298#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2299#define CAN_TDT0R_TGT_Pos (8U)
2300#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2301#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2302#define CAN_TDT0R_TIME_Pos (16U)
2303#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2304#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2305
2306/****************** Bit definition for CAN_TDL0R register *******************/
2307#define CAN_TDL0R_DATA0_Pos (0U)
2308#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2309#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2310#define CAN_TDL0R_DATA1_Pos (8U)
2311#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2312#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2313#define CAN_TDL0R_DATA2_Pos (16U)
2314#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2315#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2316#define CAN_TDL0R_DATA3_Pos (24U)
2317#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2318#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2319
2320/****************** Bit definition for CAN_TDH0R register *******************/
2321#define CAN_TDH0R_DATA4_Pos (0U)
2322#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2323#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2324#define CAN_TDH0R_DATA5_Pos (8U)
2325#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2326#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2327#define CAN_TDH0R_DATA6_Pos (16U)
2328#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2329#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2330#define CAN_TDH0R_DATA7_Pos (24U)
2331#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2332#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2333
2334/******************* Bit definition for CAN_TI1R register *******************/
2335#define CAN_TI1R_TXRQ_Pos (0U)
2336#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2337#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2338#define CAN_TI1R_RTR_Pos (1U)
2339#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2340#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2341#define CAN_TI1R_IDE_Pos (2U)
2342#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2343#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2344#define CAN_TI1R_EXID_Pos (3U)
2345#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2346#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2347#define CAN_TI1R_STID_Pos (21U)
2348#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2349#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2350
2351/******************* Bit definition for CAN_TDT1R register ******************/
2352#define CAN_TDT1R_DLC_Pos (0U)
2353#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2354#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2355#define CAN_TDT1R_TGT_Pos (8U)
2356#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2357#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2358#define CAN_TDT1R_TIME_Pos (16U)
2359#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2360#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2361
2362/******************* Bit definition for CAN_TDL1R register ******************/
2363#define CAN_TDL1R_DATA0_Pos (0U)
2364#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2365#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2366#define CAN_TDL1R_DATA1_Pos (8U)
2367#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2368#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2369#define CAN_TDL1R_DATA2_Pos (16U)
2370#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2371#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2372#define CAN_TDL1R_DATA3_Pos (24U)
2373#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2374#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2375
2376/******************* Bit definition for CAN_TDH1R register ******************/
2377#define CAN_TDH1R_DATA4_Pos (0U)
2378#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2379#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2380#define CAN_TDH1R_DATA5_Pos (8U)
2381#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2382#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2383#define CAN_TDH1R_DATA6_Pos (16U)
2384#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2385#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2386#define CAN_TDH1R_DATA7_Pos (24U)
2387#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2388#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2389
2390/******************* Bit definition for CAN_TI2R register *******************/
2391#define CAN_TI2R_TXRQ_Pos (0U)
2392#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2393#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2394#define CAN_TI2R_RTR_Pos (1U)
2395#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2396#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2397#define CAN_TI2R_IDE_Pos (2U)
2398#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2399#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2400#define CAN_TI2R_EXID_Pos (3U)
2401#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2402#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2403#define CAN_TI2R_STID_Pos (21U)
2404#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2405#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2406
2407/******************* Bit definition for CAN_TDT2R register ******************/
2408#define CAN_TDT2R_DLC_Pos (0U)
2409#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2410#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2411#define CAN_TDT2R_TGT_Pos (8U)
2412#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2413#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2414#define CAN_TDT2R_TIME_Pos (16U)
2415#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2416#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2417
2418/******************* Bit definition for CAN_TDL2R register ******************/
2419#define CAN_TDL2R_DATA0_Pos (0U)
2420#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2421#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2422#define CAN_TDL2R_DATA1_Pos (8U)
2423#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2424#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2425#define CAN_TDL2R_DATA2_Pos (16U)
2426#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2427#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2428#define CAN_TDL2R_DATA3_Pos (24U)
2429#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2430#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2431
2432/******************* Bit definition for CAN_TDH2R register ******************/
2433#define CAN_TDH2R_DATA4_Pos (0U)
2434#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2435#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2436#define CAN_TDH2R_DATA5_Pos (8U)
2437#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2438#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2439#define CAN_TDH2R_DATA6_Pos (16U)
2440#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2441#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2442#define CAN_TDH2R_DATA7_Pos (24U)
2443#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2444#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2445
2446/******************* Bit definition for CAN_RI0R register *******************/
2447#define CAN_RI0R_RTR_Pos (1U)
2448#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2449#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2450#define CAN_RI0R_IDE_Pos (2U)
2451#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2452#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2453#define CAN_RI0R_EXID_Pos (3U)
2454#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2455#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2456#define CAN_RI0R_STID_Pos (21U)
2457#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2458#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2459
2460/******************* Bit definition for CAN_RDT0R register ******************/
2461#define CAN_RDT0R_DLC_Pos (0U)
2462#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2463#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2464#define CAN_RDT0R_FMI_Pos (8U)
2465#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2466#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2467#define CAN_RDT0R_TIME_Pos (16U)
2468#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2469#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2470
2471/******************* Bit definition for CAN_RDL0R register ******************/
2472#define CAN_RDL0R_DATA0_Pos (0U)
2473#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2474#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2475#define CAN_RDL0R_DATA1_Pos (8U)
2476#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2477#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2478#define CAN_RDL0R_DATA2_Pos (16U)
2479#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2480#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2481#define CAN_RDL0R_DATA3_Pos (24U)
2482#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2483#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2484
2485/******************* Bit definition for CAN_RDH0R register ******************/
2486#define CAN_RDH0R_DATA4_Pos (0U)
2487#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2488#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2489#define CAN_RDH0R_DATA5_Pos (8U)
2490#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2491#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2492#define CAN_RDH0R_DATA6_Pos (16U)
2493#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2494#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2495#define CAN_RDH0R_DATA7_Pos (24U)
2496#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2497#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2498
2499/******************* Bit definition for CAN_RI1R register *******************/
2500#define CAN_RI1R_RTR_Pos (1U)
2501#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2502#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2503#define CAN_RI1R_IDE_Pos (2U)
2504#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2505#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2506#define CAN_RI1R_EXID_Pos (3U)
2507#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2508#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2509#define CAN_RI1R_STID_Pos (21U)
2510#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2511#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2512
2513/******************* Bit definition for CAN_RDT1R register ******************/
2514#define CAN_RDT1R_DLC_Pos (0U)
2515#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2516#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2517#define CAN_RDT1R_FMI_Pos (8U)
2518#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2519#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2520#define CAN_RDT1R_TIME_Pos (16U)
2521#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2522#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2523
2524/******************* Bit definition for CAN_RDL1R register ******************/
2525#define CAN_RDL1R_DATA0_Pos (0U)
2526#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2527#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2528#define CAN_RDL1R_DATA1_Pos (8U)
2529#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2530#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2531#define CAN_RDL1R_DATA2_Pos (16U)
2532#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2533#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2534#define CAN_RDL1R_DATA3_Pos (24U)
2535#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2536#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2537
2538/******************* Bit definition for CAN_RDH1R register ******************/
2539#define CAN_RDH1R_DATA4_Pos (0U)
2540#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2541#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2542#define CAN_RDH1R_DATA5_Pos (8U)
2543#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2544#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2545#define CAN_RDH1R_DATA6_Pos (16U)
2546#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2547#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2548#define CAN_RDH1R_DATA7_Pos (24U)
2549#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2550#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2551
2553/******************* Bit definition for CAN_FMR register ********************/
2554#define CAN_FMR_FINIT_Pos (0U)
2555#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
2556#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
2557#define CAN_FMR_CAN2SB_Pos (8U)
2558#define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
2559#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
2560
2561/******************* Bit definition for CAN_FM1R register *******************/
2562#define CAN_FM1R_FBM_Pos (0U)
2563#define CAN_FM1R_FBM_Msk (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)
2564#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2565#define CAN_FM1R_FBM0_Pos (0U)
2566#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2567#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2568#define CAN_FM1R_FBM1_Pos (1U)
2569#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2570#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2571#define CAN_FM1R_FBM2_Pos (2U)
2572#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2573#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2574#define CAN_FM1R_FBM3_Pos (3U)
2575#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2576#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2577#define CAN_FM1R_FBM4_Pos (4U)
2578#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2579#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2580#define CAN_FM1R_FBM5_Pos (5U)
2581#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2582#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2583#define CAN_FM1R_FBM6_Pos (6U)
2584#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2585#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2586#define CAN_FM1R_FBM7_Pos (7U)
2587#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2588#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2589#define CAN_FM1R_FBM8_Pos (8U)
2590#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2591#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2592#define CAN_FM1R_FBM9_Pos (9U)
2593#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2594#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2595#define CAN_FM1R_FBM10_Pos (10U)
2596#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2597#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2598#define CAN_FM1R_FBM11_Pos (11U)
2599#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2600#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2601#define CAN_FM1R_FBM12_Pos (12U)
2602#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2603#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2604#define CAN_FM1R_FBM13_Pos (13U)
2605#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2606#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2607#define CAN_FM1R_FBM14_Pos (14U)
2608#define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)
2609#define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk
2610#define CAN_FM1R_FBM15_Pos (15U)
2611#define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)
2612#define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk
2613#define CAN_FM1R_FBM16_Pos (16U)
2614#define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)
2615#define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk
2616#define CAN_FM1R_FBM17_Pos (17U)
2617#define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)
2618#define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk
2619#define CAN_FM1R_FBM18_Pos (18U)
2620#define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)
2621#define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk
2622#define CAN_FM1R_FBM19_Pos (19U)
2623#define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)
2624#define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk
2625#define CAN_FM1R_FBM20_Pos (20U)
2626#define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)
2627#define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk
2628#define CAN_FM1R_FBM21_Pos (21U)
2629#define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)
2630#define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk
2631#define CAN_FM1R_FBM22_Pos (22U)
2632#define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)
2633#define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk
2634#define CAN_FM1R_FBM23_Pos (23U)
2635#define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)
2636#define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk
2637#define CAN_FM1R_FBM24_Pos (24U)
2638#define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)
2639#define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk
2640#define CAN_FM1R_FBM25_Pos (25U)
2641#define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)
2642#define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk
2643#define CAN_FM1R_FBM26_Pos (26U)
2644#define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)
2645#define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk
2646#define CAN_FM1R_FBM27_Pos (27U)
2647#define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)
2648#define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk
2649
2650/******************* Bit definition for CAN_FS1R register *******************/
2651#define CAN_FS1R_FSC_Pos (0U)
2652#define CAN_FS1R_FSC_Msk (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)
2653#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2654#define CAN_FS1R_FSC0_Pos (0U)
2655#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2656#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2657#define CAN_FS1R_FSC1_Pos (1U)
2658#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2659#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2660#define CAN_FS1R_FSC2_Pos (2U)
2661#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2662#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2663#define CAN_FS1R_FSC3_Pos (3U)
2664#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2665#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2666#define CAN_FS1R_FSC4_Pos (4U)
2667#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2668#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2669#define CAN_FS1R_FSC5_Pos (5U)
2670#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2671#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2672#define CAN_FS1R_FSC6_Pos (6U)
2673#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2674#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2675#define CAN_FS1R_FSC7_Pos (7U)
2676#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2677#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2678#define CAN_FS1R_FSC8_Pos (8U)
2679#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2680#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2681#define CAN_FS1R_FSC9_Pos (9U)
2682#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2683#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2684#define CAN_FS1R_FSC10_Pos (10U)
2685#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2686#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2687#define CAN_FS1R_FSC11_Pos (11U)
2688#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2689#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2690#define CAN_FS1R_FSC12_Pos (12U)
2691#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2692#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2693#define CAN_FS1R_FSC13_Pos (13U)
2694#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2695#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2696#define CAN_FS1R_FSC14_Pos (14U)
2697#define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)
2698#define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk
2699#define CAN_FS1R_FSC15_Pos (15U)
2700#define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)
2701#define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk
2702#define CAN_FS1R_FSC16_Pos (16U)
2703#define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)
2704#define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk
2705#define CAN_FS1R_FSC17_Pos (17U)
2706#define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)
2707#define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk
2708#define CAN_FS1R_FSC18_Pos (18U)
2709#define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)
2710#define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk
2711#define CAN_FS1R_FSC19_Pos (19U)
2712#define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)
2713#define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk
2714#define CAN_FS1R_FSC20_Pos (20U)
2715#define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)
2716#define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk
2717#define CAN_FS1R_FSC21_Pos (21U)
2718#define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)
2719#define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk
2720#define CAN_FS1R_FSC22_Pos (22U)
2721#define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)
2722#define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk
2723#define CAN_FS1R_FSC23_Pos (23U)
2724#define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)
2725#define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk
2726#define CAN_FS1R_FSC24_Pos (24U)
2727#define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)
2728#define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk
2729#define CAN_FS1R_FSC25_Pos (25U)
2730#define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)
2731#define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk
2732#define CAN_FS1R_FSC26_Pos (26U)
2733#define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)
2734#define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk
2735#define CAN_FS1R_FSC27_Pos (27U)
2736#define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)
2737#define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk
2738
2739/****************** Bit definition for CAN_FFA1R register *******************/
2740#define CAN_FFA1R_FFA_Pos (0U)
2741#define CAN_FFA1R_FFA_Msk (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)
2742#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2743#define CAN_FFA1R_FFA0_Pos (0U)
2744#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2745#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2746#define CAN_FFA1R_FFA1_Pos (1U)
2747#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2748#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2749#define CAN_FFA1R_FFA2_Pos (2U)
2750#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2751#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2752#define CAN_FFA1R_FFA3_Pos (3U)
2753#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2754#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2755#define CAN_FFA1R_FFA4_Pos (4U)
2756#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2757#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2758#define CAN_FFA1R_FFA5_Pos (5U)
2759#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2760#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2761#define CAN_FFA1R_FFA6_Pos (6U)
2762#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2763#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2764#define CAN_FFA1R_FFA7_Pos (7U)
2765#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2766#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2767#define CAN_FFA1R_FFA8_Pos (8U)
2768#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2769#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2770#define CAN_FFA1R_FFA9_Pos (9U)
2771#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2772#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2773#define CAN_FFA1R_FFA10_Pos (10U)
2774#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2775#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2776#define CAN_FFA1R_FFA11_Pos (11U)
2777#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2778#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2779#define CAN_FFA1R_FFA12_Pos (12U)
2780#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2781#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2782#define CAN_FFA1R_FFA13_Pos (13U)
2783#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2784#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2785#define CAN_FFA1R_FFA14_Pos (14U)
2786#define CAN_FFA1R_FFA14_Msk (0x1UL << CAN_FFA1R_FFA14_Pos)
2787#define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk
2788#define CAN_FFA1R_FFA15_Pos (15U)
2789#define CAN_FFA1R_FFA15_Msk (0x1UL << CAN_FFA1R_FFA15_Pos)
2790#define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk
2791#define CAN_FFA1R_FFA16_Pos (16U)
2792#define CAN_FFA1R_FFA16_Msk (0x1UL << CAN_FFA1R_FFA16_Pos)
2793#define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk
2794#define CAN_FFA1R_FFA17_Pos (17U)
2795#define CAN_FFA1R_FFA17_Msk (0x1UL << CAN_FFA1R_FFA17_Pos)
2796#define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk
2797#define CAN_FFA1R_FFA18_Pos (18U)
2798#define CAN_FFA1R_FFA18_Msk (0x1UL << CAN_FFA1R_FFA18_Pos)
2799#define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk
2800#define CAN_FFA1R_FFA19_Pos (19U)
2801#define CAN_FFA1R_FFA19_Msk (0x1UL << CAN_FFA1R_FFA19_Pos)
2802#define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk
2803#define CAN_FFA1R_FFA20_Pos (20U)
2804#define CAN_FFA1R_FFA20_Msk (0x1UL << CAN_FFA1R_FFA20_Pos)
2805#define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk
2806#define CAN_FFA1R_FFA21_Pos (21U)
2807#define CAN_FFA1R_FFA21_Msk (0x1UL << CAN_FFA1R_FFA21_Pos)
2808#define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk
2809#define CAN_FFA1R_FFA22_Pos (22U)
2810#define CAN_FFA1R_FFA22_Msk (0x1UL << CAN_FFA1R_FFA22_Pos)
2811#define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk
2812#define CAN_FFA1R_FFA23_Pos (23U)
2813#define CAN_FFA1R_FFA23_Msk (0x1UL << CAN_FFA1R_FFA23_Pos)
2814#define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk
2815#define CAN_FFA1R_FFA24_Pos (24U)
2816#define CAN_FFA1R_FFA24_Msk (0x1UL << CAN_FFA1R_FFA24_Pos)
2817#define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk
2818#define CAN_FFA1R_FFA25_Pos (25U)
2819#define CAN_FFA1R_FFA25_Msk (0x1UL << CAN_FFA1R_FFA25_Pos)
2820#define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk
2821#define CAN_FFA1R_FFA26_Pos (26U)
2822#define CAN_FFA1R_FFA26_Msk (0x1UL << CAN_FFA1R_FFA26_Pos)
2823#define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk
2824#define CAN_FFA1R_FFA27_Pos (27U)
2825#define CAN_FFA1R_FFA27_Msk (0x1UL << CAN_FFA1R_FFA27_Pos)
2826#define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk
2827
2828/******************* Bit definition for CAN_FA1R register *******************/
2829#define CAN_FA1R_FACT_Pos (0U)
2830#define CAN_FA1R_FACT_Msk (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)
2831#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2832#define CAN_FA1R_FACT0_Pos (0U)
2833#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2834#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2835#define CAN_FA1R_FACT1_Pos (1U)
2836#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2837#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2838#define CAN_FA1R_FACT2_Pos (2U)
2839#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2840#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2841#define CAN_FA1R_FACT3_Pos (3U)
2842#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2843#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2844#define CAN_FA1R_FACT4_Pos (4U)
2845#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2846#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2847#define CAN_FA1R_FACT5_Pos (5U)
2848#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2849#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2850#define CAN_FA1R_FACT6_Pos (6U)
2851#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2852#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2853#define CAN_FA1R_FACT7_Pos (7U)
2854#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2855#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2856#define CAN_FA1R_FACT8_Pos (8U)
2857#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2858#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2859#define CAN_FA1R_FACT9_Pos (9U)
2860#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2861#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2862#define CAN_FA1R_FACT10_Pos (10U)
2863#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2864#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2865#define CAN_FA1R_FACT11_Pos (11U)
2866#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2867#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2868#define CAN_FA1R_FACT12_Pos (12U)
2869#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2870#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2871#define CAN_FA1R_FACT13_Pos (13U)
2872#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2873#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2874#define CAN_FA1R_FACT14_Pos (14U)
2875#define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)
2876#define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk
2877#define CAN_FA1R_FACT15_Pos (15U)
2878#define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)
2879#define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk
2880#define CAN_FA1R_FACT16_Pos (16U)
2881#define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)
2882#define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk
2883#define CAN_FA1R_FACT17_Pos (17U)
2884#define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)
2885#define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk
2886#define CAN_FA1R_FACT18_Pos (18U)
2887#define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)
2888#define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk
2889#define CAN_FA1R_FACT19_Pos (19U)
2890#define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)
2891#define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk
2892#define CAN_FA1R_FACT20_Pos (20U)
2893#define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)
2894#define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk
2895#define CAN_FA1R_FACT21_Pos (21U)
2896#define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)
2897#define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk
2898#define CAN_FA1R_FACT22_Pos (22U)
2899#define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)
2900#define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk
2901#define CAN_FA1R_FACT23_Pos (23U)
2902#define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)
2903#define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk
2904#define CAN_FA1R_FACT24_Pos (24U)
2905#define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)
2906#define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk
2907#define CAN_FA1R_FACT25_Pos (25U)
2908#define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)
2909#define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk
2910#define CAN_FA1R_FACT26_Pos (26U)
2911#define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)
2912#define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk
2913#define CAN_FA1R_FACT27_Pos (27U)
2914#define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)
2915#define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk
2916
2917
2918/******************* Bit definition for CAN_F0R1 register *******************/
2919#define CAN_F0R1_FB0_Pos (0U)
2920#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2921#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2922#define CAN_F0R1_FB1_Pos (1U)
2923#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2924#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2925#define CAN_F0R1_FB2_Pos (2U)
2926#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2927#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2928#define CAN_F0R1_FB3_Pos (3U)
2929#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2930#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2931#define CAN_F0R1_FB4_Pos (4U)
2932#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2933#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2934#define CAN_F0R1_FB5_Pos (5U)
2935#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2936#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2937#define CAN_F0R1_FB6_Pos (6U)
2938#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2939#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2940#define CAN_F0R1_FB7_Pos (7U)
2941#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2942#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2943#define CAN_F0R1_FB8_Pos (8U)
2944#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2945#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2946#define CAN_F0R1_FB9_Pos (9U)
2947#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2948#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2949#define CAN_F0R1_FB10_Pos (10U)
2950#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2951#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2952#define CAN_F0R1_FB11_Pos (11U)
2953#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2954#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2955#define CAN_F0R1_FB12_Pos (12U)
2956#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2957#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2958#define CAN_F0R1_FB13_Pos (13U)
2959#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2960#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2961#define CAN_F0R1_FB14_Pos (14U)
2962#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2963#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2964#define CAN_F0R1_FB15_Pos (15U)
2965#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2966#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2967#define CAN_F0R1_FB16_Pos (16U)
2968#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2969#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2970#define CAN_F0R1_FB17_Pos (17U)
2971#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2972#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2973#define CAN_F0R1_FB18_Pos (18U)
2974#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2975#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2976#define CAN_F0R1_FB19_Pos (19U)
2977#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2978#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2979#define CAN_F0R1_FB20_Pos (20U)
2980#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2981#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2982#define CAN_F0R1_FB21_Pos (21U)
2983#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2984#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2985#define CAN_F0R1_FB22_Pos (22U)
2986#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2987#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2988#define CAN_F0R1_FB23_Pos (23U)
2989#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2990#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2991#define CAN_F0R1_FB24_Pos (24U)
2992#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2993#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2994#define CAN_F0R1_FB25_Pos (25U)
2995#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2996#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2997#define CAN_F0R1_FB26_Pos (26U)
2998#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2999#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
3000#define CAN_F0R1_FB27_Pos (27U)
3001#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
3002#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
3003#define CAN_F0R1_FB28_Pos (28U)
3004#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
3005#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
3006#define CAN_F0R1_FB29_Pos (29U)
3007#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
3008#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
3009#define CAN_F0R1_FB30_Pos (30U)
3010#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
3011#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
3012#define CAN_F0R1_FB31_Pos (31U)
3013#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
3014#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
3015
3016/******************* Bit definition for CAN_F1R1 register *******************/
3017#define CAN_F1R1_FB0_Pos (0U)
3018#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
3019#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
3020#define CAN_F1R1_FB1_Pos (1U)
3021#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
3022#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
3023#define CAN_F1R1_FB2_Pos (2U)
3024#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
3025#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
3026#define CAN_F1R1_FB3_Pos (3U)
3027#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
3028#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
3029#define CAN_F1R1_FB4_Pos (4U)
3030#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
3031#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
3032#define CAN_F1R1_FB5_Pos (5U)
3033#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
3034#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
3035#define CAN_F1R1_FB6_Pos (6U)
3036#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
3037#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
3038#define CAN_F1R1_FB7_Pos (7U)
3039#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
3040#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
3041#define CAN_F1R1_FB8_Pos (8U)
3042#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
3043#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
3044#define CAN_F1R1_FB9_Pos (9U)
3045#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
3046#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
3047#define CAN_F1R1_FB10_Pos (10U)
3048#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
3049#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
3050#define CAN_F1R1_FB11_Pos (11U)
3051#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
3052#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
3053#define CAN_F1R1_FB12_Pos (12U)
3054#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
3055#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
3056#define CAN_F1R1_FB13_Pos (13U)
3057#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
3058#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
3059#define CAN_F1R1_FB14_Pos (14U)
3060#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
3061#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
3062#define CAN_F1R1_FB15_Pos (15U)
3063#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
3064#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
3065#define CAN_F1R1_FB16_Pos (16U)
3066#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
3067#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
3068#define CAN_F1R1_FB17_Pos (17U)
3069#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
3070#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
3071#define CAN_F1R1_FB18_Pos (18U)
3072#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
3073#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
3074#define CAN_F1R1_FB19_Pos (19U)
3075#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
3076#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
3077#define CAN_F1R1_FB20_Pos (20U)
3078#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
3079#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
3080#define CAN_F1R1_FB21_Pos (21U)
3081#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
3082#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
3083#define CAN_F1R1_FB22_Pos (22U)
3084#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
3085#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
3086#define CAN_F1R1_FB23_Pos (23U)
3087#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
3088#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
3089#define CAN_F1R1_FB24_Pos (24U)
3090#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
3091#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
3092#define CAN_F1R1_FB25_Pos (25U)
3093#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
3094#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
3095#define CAN_F1R1_FB26_Pos (26U)
3096#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
3097#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
3098#define CAN_F1R1_FB27_Pos (27U)
3099#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
3100#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
3101#define CAN_F1R1_FB28_Pos (28U)
3102#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
3103#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
3104#define CAN_F1R1_FB29_Pos (29U)
3105#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
3106#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
3107#define CAN_F1R1_FB30_Pos (30U)
3108#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
3109#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
3110#define CAN_F1R1_FB31_Pos (31U)
3111#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
3112#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
3113
3114/******************* Bit definition for CAN_F2R1 register *******************/
3115#define CAN_F2R1_FB0_Pos (0U)
3116#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
3117#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
3118#define CAN_F2R1_FB1_Pos (1U)
3119#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
3120#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
3121#define CAN_F2R1_FB2_Pos (2U)
3122#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
3123#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
3124#define CAN_F2R1_FB3_Pos (3U)
3125#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
3126#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
3127#define CAN_F2R1_FB4_Pos (4U)
3128#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
3129#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
3130#define CAN_F2R1_FB5_Pos (5U)
3131#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
3132#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
3133#define CAN_F2R1_FB6_Pos (6U)
3134#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
3135#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
3136#define CAN_F2R1_FB7_Pos (7U)
3137#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
3138#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
3139#define CAN_F2R1_FB8_Pos (8U)
3140#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
3141#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
3142#define CAN_F2R1_FB9_Pos (9U)
3143#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
3144#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
3145#define CAN_F2R1_FB10_Pos (10U)
3146#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
3147#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
3148#define CAN_F2R1_FB11_Pos (11U)
3149#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
3150#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
3151#define CAN_F2R1_FB12_Pos (12U)
3152#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
3153#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
3154#define CAN_F2R1_FB13_Pos (13U)
3155#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
3156#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
3157#define CAN_F2R1_FB14_Pos (14U)
3158#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
3159#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
3160#define CAN_F2R1_FB15_Pos (15U)
3161#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
3162#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
3163#define CAN_F2R1_FB16_Pos (16U)
3164#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
3165#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
3166#define CAN_F2R1_FB17_Pos (17U)
3167#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
3168#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
3169#define CAN_F2R1_FB18_Pos (18U)
3170#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
3171#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
3172#define CAN_F2R1_FB19_Pos (19U)
3173#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
3174#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
3175#define CAN_F2R1_FB20_Pos (20U)
3176#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
3177#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
3178#define CAN_F2R1_FB21_Pos (21U)
3179#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
3180#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
3181#define CAN_F2R1_FB22_Pos (22U)
3182#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
3183#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
3184#define CAN_F2R1_FB23_Pos (23U)
3185#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
3186#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
3187#define CAN_F2R1_FB24_Pos (24U)
3188#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
3189#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
3190#define CAN_F2R1_FB25_Pos (25U)
3191#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
3192#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
3193#define CAN_F2R1_FB26_Pos (26U)
3194#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
3195#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
3196#define CAN_F2R1_FB27_Pos (27U)
3197#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
3198#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
3199#define CAN_F2R1_FB28_Pos (28U)
3200#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
3201#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
3202#define CAN_F2R1_FB29_Pos (29U)
3203#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
3204#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
3205#define CAN_F2R1_FB30_Pos (30U)
3206#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
3207#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
3208#define CAN_F2R1_FB31_Pos (31U)
3209#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
3210#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
3211
3212/******************* Bit definition for CAN_F3R1 register *******************/
3213#define CAN_F3R1_FB0_Pos (0U)
3214#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
3215#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
3216#define CAN_F3R1_FB1_Pos (1U)
3217#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
3218#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
3219#define CAN_F3R1_FB2_Pos (2U)
3220#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
3221#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
3222#define CAN_F3R1_FB3_Pos (3U)
3223#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
3224#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
3225#define CAN_F3R1_FB4_Pos (4U)
3226#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
3227#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
3228#define CAN_F3R1_FB5_Pos (5U)
3229#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
3230#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
3231#define CAN_F3R1_FB6_Pos (6U)
3232#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
3233#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
3234#define CAN_F3R1_FB7_Pos (7U)
3235#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
3236#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
3237#define CAN_F3R1_FB8_Pos (8U)
3238#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
3239#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
3240#define CAN_F3R1_FB9_Pos (9U)
3241#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
3242#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
3243#define CAN_F3R1_FB10_Pos (10U)
3244#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
3245#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
3246#define CAN_F3R1_FB11_Pos (11U)
3247#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
3248#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
3249#define CAN_F3R1_FB12_Pos (12U)
3250#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
3251#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
3252#define CAN_F3R1_FB13_Pos (13U)
3253#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
3254#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
3255#define CAN_F3R1_FB14_Pos (14U)
3256#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
3257#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
3258#define CAN_F3R1_FB15_Pos (15U)
3259#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
3260#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
3261#define CAN_F3R1_FB16_Pos (16U)
3262#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
3263#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
3264#define CAN_F3R1_FB17_Pos (17U)
3265#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
3266#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
3267#define CAN_F3R1_FB18_Pos (18U)
3268#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
3269#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
3270#define CAN_F3R1_FB19_Pos (19U)
3271#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
3272#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
3273#define CAN_F3R1_FB20_Pos (20U)
3274#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
3275#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
3276#define CAN_F3R1_FB21_Pos (21U)
3277#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
3278#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
3279#define CAN_F3R1_FB22_Pos (22U)
3280#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
3281#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
3282#define CAN_F3R1_FB23_Pos (23U)
3283#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
3284#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
3285#define CAN_F3R1_FB24_Pos (24U)
3286#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
3287#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
3288#define CAN_F3R1_FB25_Pos (25U)
3289#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
3290#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
3291#define CAN_F3R1_FB26_Pos (26U)
3292#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
3293#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
3294#define CAN_F3R1_FB27_Pos (27U)
3295#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
3296#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
3297#define CAN_F3R1_FB28_Pos (28U)
3298#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
3299#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
3300#define CAN_F3R1_FB29_Pos (29U)
3301#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
3302#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
3303#define CAN_F3R1_FB30_Pos (30U)
3304#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
3305#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
3306#define CAN_F3R1_FB31_Pos (31U)
3307#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
3308#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
3309
3310/******************* Bit definition for CAN_F4R1 register *******************/
3311#define CAN_F4R1_FB0_Pos (0U)
3312#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
3313#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
3314#define CAN_F4R1_FB1_Pos (1U)
3315#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
3316#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
3317#define CAN_F4R1_FB2_Pos (2U)
3318#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
3319#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
3320#define CAN_F4R1_FB3_Pos (3U)
3321#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
3322#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
3323#define CAN_F4R1_FB4_Pos (4U)
3324#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
3325#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
3326#define CAN_F4R1_FB5_Pos (5U)
3327#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
3328#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
3329#define CAN_F4R1_FB6_Pos (6U)
3330#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
3331#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
3332#define CAN_F4R1_FB7_Pos (7U)
3333#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
3334#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
3335#define CAN_F4R1_FB8_Pos (8U)
3336#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
3337#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
3338#define CAN_F4R1_FB9_Pos (9U)
3339#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
3340#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
3341#define CAN_F4R1_FB10_Pos (10U)
3342#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
3343#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
3344#define CAN_F4R1_FB11_Pos (11U)
3345#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
3346#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
3347#define CAN_F4R1_FB12_Pos (12U)
3348#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
3349#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
3350#define CAN_F4R1_FB13_Pos (13U)
3351#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
3352#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
3353#define CAN_F4R1_FB14_Pos (14U)
3354#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
3355#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
3356#define CAN_F4R1_FB15_Pos (15U)
3357#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
3358#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
3359#define CAN_F4R1_FB16_Pos (16U)
3360#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
3361#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
3362#define CAN_F4R1_FB17_Pos (17U)
3363#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
3364#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
3365#define CAN_F4R1_FB18_Pos (18U)
3366#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
3367#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
3368#define CAN_F4R1_FB19_Pos (19U)
3369#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
3370#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
3371#define CAN_F4R1_FB20_Pos (20U)
3372#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
3373#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
3374#define CAN_F4R1_FB21_Pos (21U)
3375#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
3376#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
3377#define CAN_F4R1_FB22_Pos (22U)
3378#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
3379#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
3380#define CAN_F4R1_FB23_Pos (23U)
3381#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
3382#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
3383#define CAN_F4R1_FB24_Pos (24U)
3384#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
3385#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
3386#define CAN_F4R1_FB25_Pos (25U)
3387#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
3388#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
3389#define CAN_F4R1_FB26_Pos (26U)
3390#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
3391#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
3392#define CAN_F4R1_FB27_Pos (27U)
3393#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
3394#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
3395#define CAN_F4R1_FB28_Pos (28U)
3396#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
3397#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
3398#define CAN_F4R1_FB29_Pos (29U)
3399#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
3400#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
3401#define CAN_F4R1_FB30_Pos (30U)
3402#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
3403#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
3404#define CAN_F4R1_FB31_Pos (31U)
3405#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
3406#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
3407
3408/******************* Bit definition for CAN_F5R1 register *******************/
3409#define CAN_F5R1_FB0_Pos (0U)
3410#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
3411#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
3412#define CAN_F5R1_FB1_Pos (1U)
3413#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
3414#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
3415#define CAN_F5R1_FB2_Pos (2U)
3416#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3417#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3418#define CAN_F5R1_FB3_Pos (3U)
3419#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3420#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3421#define CAN_F5R1_FB4_Pos (4U)
3422#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3423#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3424#define CAN_F5R1_FB5_Pos (5U)
3425#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3426#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3427#define CAN_F5R1_FB6_Pos (6U)
3428#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3429#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3430#define CAN_F5R1_FB7_Pos (7U)
3431#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3432#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3433#define CAN_F5R1_FB8_Pos (8U)
3434#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3435#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3436#define CAN_F5R1_FB9_Pos (9U)
3437#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3438#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3439#define CAN_F5R1_FB10_Pos (10U)
3440#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3441#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3442#define CAN_F5R1_FB11_Pos (11U)
3443#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3444#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3445#define CAN_F5R1_FB12_Pos (12U)
3446#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3447#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3448#define CAN_F5R1_FB13_Pos (13U)
3449#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3450#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3451#define CAN_F5R1_FB14_Pos (14U)
3452#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3453#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3454#define CAN_F5R1_FB15_Pos (15U)
3455#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3456#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3457#define CAN_F5R1_FB16_Pos (16U)
3458#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3459#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3460#define CAN_F5R1_FB17_Pos (17U)
3461#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3462#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3463#define CAN_F5R1_FB18_Pos (18U)
3464#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3465#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3466#define CAN_F5R1_FB19_Pos (19U)
3467#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3468#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3469#define CAN_F5R1_FB20_Pos (20U)
3470#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3471#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3472#define CAN_F5R1_FB21_Pos (21U)
3473#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3474#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3475#define CAN_F5R1_FB22_Pos (22U)
3476#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3477#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3478#define CAN_F5R1_FB23_Pos (23U)
3479#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3480#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3481#define CAN_F5R1_FB24_Pos (24U)
3482#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3483#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3484#define CAN_F5R1_FB25_Pos (25U)
3485#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3486#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3487#define CAN_F5R1_FB26_Pos (26U)
3488#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3489#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3490#define CAN_F5R1_FB27_Pos (27U)
3491#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3492#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3493#define CAN_F5R1_FB28_Pos (28U)
3494#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3495#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3496#define CAN_F5R1_FB29_Pos (29U)
3497#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3498#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3499#define CAN_F5R1_FB30_Pos (30U)
3500#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3501#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3502#define CAN_F5R1_FB31_Pos (31U)
3503#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3504#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3505
3506/******************* Bit definition for CAN_F6R1 register *******************/
3507#define CAN_F6R1_FB0_Pos (0U)
3508#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3509#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3510#define CAN_F6R1_FB1_Pos (1U)
3511#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3512#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3513#define CAN_F6R1_FB2_Pos (2U)
3514#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3515#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3516#define CAN_F6R1_FB3_Pos (3U)
3517#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3518#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3519#define CAN_F6R1_FB4_Pos (4U)
3520#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3521#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3522#define CAN_F6R1_FB5_Pos (5U)
3523#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3524#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3525#define CAN_F6R1_FB6_Pos (6U)
3526#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3527#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3528#define CAN_F6R1_FB7_Pos (7U)
3529#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3530#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3531#define CAN_F6R1_FB8_Pos (8U)
3532#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3533#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3534#define CAN_F6R1_FB9_Pos (9U)
3535#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3536#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3537#define CAN_F6R1_FB10_Pos (10U)
3538#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3539#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3540#define CAN_F6R1_FB11_Pos (11U)
3541#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3542#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3543#define CAN_F6R1_FB12_Pos (12U)
3544#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3545#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3546#define CAN_F6R1_FB13_Pos (13U)
3547#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3548#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3549#define CAN_F6R1_FB14_Pos (14U)
3550#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3551#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3552#define CAN_F6R1_FB15_Pos (15U)
3553#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3554#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3555#define CAN_F6R1_FB16_Pos (16U)
3556#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3557#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3558#define CAN_F6R1_FB17_Pos (17U)
3559#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3560#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3561#define CAN_F6R1_FB18_Pos (18U)
3562#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3563#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3564#define CAN_F6R1_FB19_Pos (19U)
3565#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3566#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3567#define CAN_F6R1_FB20_Pos (20U)
3568#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3569#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3570#define CAN_F6R1_FB21_Pos (21U)
3571#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3572#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3573#define CAN_F6R1_FB22_Pos (22U)
3574#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3575#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3576#define CAN_F6R1_FB23_Pos (23U)
3577#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3578#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3579#define CAN_F6R1_FB24_Pos (24U)
3580#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3581#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3582#define CAN_F6R1_FB25_Pos (25U)
3583#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3584#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3585#define CAN_F6R1_FB26_Pos (26U)
3586#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3587#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3588#define CAN_F6R1_FB27_Pos (27U)
3589#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3590#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3591#define CAN_F6R1_FB28_Pos (28U)
3592#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3593#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3594#define CAN_F6R1_FB29_Pos (29U)
3595#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3596#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3597#define CAN_F6R1_FB30_Pos (30U)
3598#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3599#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3600#define CAN_F6R1_FB31_Pos (31U)
3601#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3602#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3603
3604/******************* Bit definition for CAN_F7R1 register *******************/
3605#define CAN_F7R1_FB0_Pos (0U)
3606#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3607#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3608#define CAN_F7R1_FB1_Pos (1U)
3609#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3610#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3611#define CAN_F7R1_FB2_Pos (2U)
3612#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3613#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3614#define CAN_F7R1_FB3_Pos (3U)
3615#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3616#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3617#define CAN_F7R1_FB4_Pos (4U)
3618#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3619#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3620#define CAN_F7R1_FB5_Pos (5U)
3621#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3622#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3623#define CAN_F7R1_FB6_Pos (6U)
3624#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3625#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3626#define CAN_F7R1_FB7_Pos (7U)
3627#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3628#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3629#define CAN_F7R1_FB8_Pos (8U)
3630#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3631#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3632#define CAN_F7R1_FB9_Pos (9U)
3633#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3634#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3635#define CAN_F7R1_FB10_Pos (10U)
3636#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3637#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3638#define CAN_F7R1_FB11_Pos (11U)
3639#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3640#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3641#define CAN_F7R1_FB12_Pos (12U)
3642#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3643#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3644#define CAN_F7R1_FB13_Pos (13U)
3645#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3646#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3647#define CAN_F7R1_FB14_Pos (14U)
3648#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3649#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3650#define CAN_F7R1_FB15_Pos (15U)
3651#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3652#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3653#define CAN_F7R1_FB16_Pos (16U)
3654#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3655#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3656#define CAN_F7R1_FB17_Pos (17U)
3657#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3658#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3659#define CAN_F7R1_FB18_Pos (18U)
3660#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3661#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3662#define CAN_F7R1_FB19_Pos (19U)
3663#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3664#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3665#define CAN_F7R1_FB20_Pos (20U)
3666#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3667#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3668#define CAN_F7R1_FB21_Pos (21U)
3669#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3670#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3671#define CAN_F7R1_FB22_Pos (22U)
3672#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3673#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3674#define CAN_F7R1_FB23_Pos (23U)
3675#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3676#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3677#define CAN_F7R1_FB24_Pos (24U)
3678#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3679#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3680#define CAN_F7R1_FB25_Pos (25U)
3681#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3682#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3683#define CAN_F7R1_FB26_Pos (26U)
3684#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3685#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3686#define CAN_F7R1_FB27_Pos (27U)
3687#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3688#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3689#define CAN_F7R1_FB28_Pos (28U)
3690#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3691#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3692#define CAN_F7R1_FB29_Pos (29U)
3693#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3694#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3695#define CAN_F7R1_FB30_Pos (30U)
3696#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3697#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3698#define CAN_F7R1_FB31_Pos (31U)
3699#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3700#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3701
3702/******************* Bit definition for CAN_F8R1 register *******************/
3703#define CAN_F8R1_FB0_Pos (0U)
3704#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3705#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3706#define CAN_F8R1_FB1_Pos (1U)
3707#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3708#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3709#define CAN_F8R1_FB2_Pos (2U)
3710#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3711#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3712#define CAN_F8R1_FB3_Pos (3U)
3713#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3714#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3715#define CAN_F8R1_FB4_Pos (4U)
3716#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3717#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3718#define CAN_F8R1_FB5_Pos (5U)
3719#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3720#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3721#define CAN_F8R1_FB6_Pos (6U)
3722#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3723#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3724#define CAN_F8R1_FB7_Pos (7U)
3725#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3726#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3727#define CAN_F8R1_FB8_Pos (8U)
3728#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3729#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3730#define CAN_F8R1_FB9_Pos (9U)
3731#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3732#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3733#define CAN_F8R1_FB10_Pos (10U)
3734#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3735#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3736#define CAN_F8R1_FB11_Pos (11U)
3737#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3738#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3739#define CAN_F8R1_FB12_Pos (12U)
3740#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3741#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3742#define CAN_F8R1_FB13_Pos (13U)
3743#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3744#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3745#define CAN_F8R1_FB14_Pos (14U)
3746#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3747#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3748#define CAN_F8R1_FB15_Pos (15U)
3749#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3750#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3751#define CAN_F8R1_FB16_Pos (16U)
3752#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3753#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3754#define CAN_F8R1_FB17_Pos (17U)
3755#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3756#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3757#define CAN_F8R1_FB18_Pos (18U)
3758#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3759#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3760#define CAN_F8R1_FB19_Pos (19U)
3761#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3762#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3763#define CAN_F8R1_FB20_Pos (20U)
3764#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3765#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3766#define CAN_F8R1_FB21_Pos (21U)
3767#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3768#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3769#define CAN_F8R1_FB22_Pos (22U)
3770#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3771#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3772#define CAN_F8R1_FB23_Pos (23U)
3773#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3774#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3775#define CAN_F8R1_FB24_Pos (24U)
3776#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3777#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3778#define CAN_F8R1_FB25_Pos (25U)
3779#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3780#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3781#define CAN_F8R1_FB26_Pos (26U)
3782#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3783#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3784#define CAN_F8R1_FB27_Pos (27U)
3785#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3786#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3787#define CAN_F8R1_FB28_Pos (28U)
3788#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3789#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3790#define CAN_F8R1_FB29_Pos (29U)
3791#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3792#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3793#define CAN_F8R1_FB30_Pos (30U)
3794#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3795#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3796#define CAN_F8R1_FB31_Pos (31U)
3797#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3798#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3799
3800/******************* Bit definition for CAN_F9R1 register *******************/
3801#define CAN_F9R1_FB0_Pos (0U)
3802#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3803#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3804#define CAN_F9R1_FB1_Pos (1U)
3805#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3806#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3807#define CAN_F9R1_FB2_Pos (2U)
3808#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3809#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3810#define CAN_F9R1_FB3_Pos (3U)
3811#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3812#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3813#define CAN_F9R1_FB4_Pos (4U)
3814#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3815#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3816#define CAN_F9R1_FB5_Pos (5U)
3817#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3818#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3819#define CAN_F9R1_FB6_Pos (6U)
3820#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3821#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3822#define CAN_F9R1_FB7_Pos (7U)
3823#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3824#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3825#define CAN_F9R1_FB8_Pos (8U)
3826#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3827#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3828#define CAN_F9R1_FB9_Pos (9U)
3829#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3830#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3831#define CAN_F9R1_FB10_Pos (10U)
3832#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3833#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3834#define CAN_F9R1_FB11_Pos (11U)
3835#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3836#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3837#define CAN_F9R1_FB12_Pos (12U)
3838#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3839#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3840#define CAN_F9R1_FB13_Pos (13U)
3841#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3842#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3843#define CAN_F9R1_FB14_Pos (14U)
3844#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3845#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3846#define CAN_F9R1_FB15_Pos (15U)
3847#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3848#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3849#define CAN_F9R1_FB16_Pos (16U)
3850#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3851#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3852#define CAN_F9R1_FB17_Pos (17U)
3853#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3854#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3855#define CAN_F9R1_FB18_Pos (18U)
3856#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3857#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3858#define CAN_F9R1_FB19_Pos (19U)
3859#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3860#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3861#define CAN_F9R1_FB20_Pos (20U)
3862#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3863#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3864#define CAN_F9R1_FB21_Pos (21U)
3865#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3866#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3867#define CAN_F9R1_FB22_Pos (22U)
3868#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3869#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3870#define CAN_F9R1_FB23_Pos (23U)
3871#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3872#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3873#define CAN_F9R1_FB24_Pos (24U)
3874#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3875#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3876#define CAN_F9R1_FB25_Pos (25U)
3877#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3878#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3879#define CAN_F9R1_FB26_Pos (26U)
3880#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3881#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3882#define CAN_F9R1_FB27_Pos (27U)
3883#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3884#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3885#define CAN_F9R1_FB28_Pos (28U)
3886#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3887#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3888#define CAN_F9R1_FB29_Pos (29U)
3889#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3890#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3891#define CAN_F9R1_FB30_Pos (30U)
3892#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3893#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3894#define CAN_F9R1_FB31_Pos (31U)
3895#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3896#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3897
3898/******************* Bit definition for CAN_F10R1 register ******************/
3899#define CAN_F10R1_FB0_Pos (0U)
3900#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3901#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3902#define CAN_F10R1_FB1_Pos (1U)
3903#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3904#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3905#define CAN_F10R1_FB2_Pos (2U)
3906#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3907#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3908#define CAN_F10R1_FB3_Pos (3U)
3909#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3910#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3911#define CAN_F10R1_FB4_Pos (4U)
3912#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3913#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3914#define CAN_F10R1_FB5_Pos (5U)
3915#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3916#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3917#define CAN_F10R1_FB6_Pos (6U)
3918#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3919#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3920#define CAN_F10R1_FB7_Pos (7U)
3921#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3922#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3923#define CAN_F10R1_FB8_Pos (8U)
3924#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3925#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3926#define CAN_F10R1_FB9_Pos (9U)
3927#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3928#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3929#define CAN_F10R1_FB10_Pos (10U)
3930#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3931#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3932#define CAN_F10R1_FB11_Pos (11U)
3933#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3934#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3935#define CAN_F10R1_FB12_Pos (12U)
3936#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3937#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3938#define CAN_F10R1_FB13_Pos (13U)
3939#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3940#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3941#define CAN_F10R1_FB14_Pos (14U)
3942#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3943#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3944#define CAN_F10R1_FB15_Pos (15U)
3945#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3946#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3947#define CAN_F10R1_FB16_Pos (16U)
3948#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3949#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3950#define CAN_F10R1_FB17_Pos (17U)
3951#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3952#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3953#define CAN_F10R1_FB18_Pos (18U)
3954#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3955#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3956#define CAN_F10R1_FB19_Pos (19U)
3957#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3958#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3959#define CAN_F10R1_FB20_Pos (20U)
3960#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3961#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3962#define CAN_F10R1_FB21_Pos (21U)
3963#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3964#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3965#define CAN_F10R1_FB22_Pos (22U)
3966#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3967#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3968#define CAN_F10R1_FB23_Pos (23U)
3969#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3970#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3971#define CAN_F10R1_FB24_Pos (24U)
3972#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3973#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3974#define CAN_F10R1_FB25_Pos (25U)
3975#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3976#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3977#define CAN_F10R1_FB26_Pos (26U)
3978#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3979#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3980#define CAN_F10R1_FB27_Pos (27U)
3981#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3982#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3983#define CAN_F10R1_FB28_Pos (28U)
3984#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3985#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3986#define CAN_F10R1_FB29_Pos (29U)
3987#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3988#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3989#define CAN_F10R1_FB30_Pos (30U)
3990#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3991#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3992#define CAN_F10R1_FB31_Pos (31U)
3993#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3994#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3995
3996/******************* Bit definition for CAN_F11R1 register ******************/
3997#define CAN_F11R1_FB0_Pos (0U)
3998#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3999#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
4000#define CAN_F11R1_FB1_Pos (1U)
4001#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
4002#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
4003#define CAN_F11R1_FB2_Pos (2U)
4004#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
4005#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
4006#define CAN_F11R1_FB3_Pos (3U)
4007#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
4008#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
4009#define CAN_F11R1_FB4_Pos (4U)
4010#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
4011#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
4012#define CAN_F11R1_FB5_Pos (5U)
4013#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
4014#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
4015#define CAN_F11R1_FB6_Pos (6U)
4016#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
4017#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
4018#define CAN_F11R1_FB7_Pos (7U)
4019#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
4020#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
4021#define CAN_F11R1_FB8_Pos (8U)
4022#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
4023#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
4024#define CAN_F11R1_FB9_Pos (9U)
4025#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
4026#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
4027#define CAN_F11R1_FB10_Pos (10U)
4028#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
4029#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
4030#define CAN_F11R1_FB11_Pos (11U)
4031#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
4032#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
4033#define CAN_F11R1_FB12_Pos (12U)
4034#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
4035#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
4036#define CAN_F11R1_FB13_Pos (13U)
4037#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
4038#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
4039#define CAN_F11R1_FB14_Pos (14U)
4040#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
4041#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
4042#define CAN_F11R1_FB15_Pos (15U)
4043#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
4044#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
4045#define CAN_F11R1_FB16_Pos (16U)
4046#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
4047#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
4048#define CAN_F11R1_FB17_Pos (17U)
4049#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
4050#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
4051#define CAN_F11R1_FB18_Pos (18U)
4052#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
4053#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
4054#define CAN_F11R1_FB19_Pos (19U)
4055#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
4056#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
4057#define CAN_F11R1_FB20_Pos (20U)
4058#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
4059#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
4060#define CAN_F11R1_FB21_Pos (21U)
4061#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
4062#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
4063#define CAN_F11R1_FB22_Pos (22U)
4064#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
4065#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
4066#define CAN_F11R1_FB23_Pos (23U)
4067#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
4068#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
4069#define CAN_F11R1_FB24_Pos (24U)
4070#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
4071#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
4072#define CAN_F11R1_FB25_Pos (25U)
4073#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
4074#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
4075#define CAN_F11R1_FB26_Pos (26U)
4076#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
4077#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
4078#define CAN_F11R1_FB27_Pos (27U)
4079#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
4080#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
4081#define CAN_F11R1_FB28_Pos (28U)
4082#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
4083#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
4084#define CAN_F11R1_FB29_Pos (29U)
4085#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
4086#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
4087#define CAN_F11R1_FB30_Pos (30U)
4088#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
4089#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
4090#define CAN_F11R1_FB31_Pos (31U)
4091#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
4092#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
4093
4094/******************* Bit definition for CAN_F12R1 register ******************/
4095#define CAN_F12R1_FB0_Pos (0U)
4096#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
4097#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
4098#define CAN_F12R1_FB1_Pos (1U)
4099#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
4100#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
4101#define CAN_F12R1_FB2_Pos (2U)
4102#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
4103#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
4104#define CAN_F12R1_FB3_Pos (3U)
4105#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
4106#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
4107#define CAN_F12R1_FB4_Pos (4U)
4108#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
4109#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
4110#define CAN_F12R1_FB5_Pos (5U)
4111#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
4112#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
4113#define CAN_F12R1_FB6_Pos (6U)
4114#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
4115#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
4116#define CAN_F12R1_FB7_Pos (7U)
4117#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
4118#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
4119#define CAN_F12R1_FB8_Pos (8U)
4120#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
4121#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
4122#define CAN_F12R1_FB9_Pos (9U)
4123#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
4124#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
4125#define CAN_F12R1_FB10_Pos (10U)
4126#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
4127#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
4128#define CAN_F12R1_FB11_Pos (11U)
4129#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
4130#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
4131#define CAN_F12R1_FB12_Pos (12U)
4132#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
4133#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
4134#define CAN_F12R1_FB13_Pos (13U)
4135#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
4136#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
4137#define CAN_F12R1_FB14_Pos (14U)
4138#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
4139#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
4140#define CAN_F12R1_FB15_Pos (15U)
4141#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
4142#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
4143#define CAN_F12R1_FB16_Pos (16U)
4144#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
4145#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
4146#define CAN_F12R1_FB17_Pos (17U)
4147#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
4148#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
4149#define CAN_F12R1_FB18_Pos (18U)
4150#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
4151#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
4152#define CAN_F12R1_FB19_Pos (19U)
4153#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
4154#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
4155#define CAN_F12R1_FB20_Pos (20U)
4156#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
4157#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
4158#define CAN_F12R1_FB21_Pos (21U)
4159#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
4160#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
4161#define CAN_F12R1_FB22_Pos (22U)
4162#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
4163#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
4164#define CAN_F12R1_FB23_Pos (23U)
4165#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
4166#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
4167#define CAN_F12R1_FB24_Pos (24U)
4168#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
4169#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
4170#define CAN_F12R1_FB25_Pos (25U)
4171#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
4172#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
4173#define CAN_F12R1_FB26_Pos (26U)
4174#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
4175#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
4176#define CAN_F12R1_FB27_Pos (27U)
4177#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
4178#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
4179#define CAN_F12R1_FB28_Pos (28U)
4180#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
4181#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
4182#define CAN_F12R1_FB29_Pos (29U)
4183#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
4184#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
4185#define CAN_F12R1_FB30_Pos (30U)
4186#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
4187#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
4188#define CAN_F12R1_FB31_Pos (31U)
4189#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
4190#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
4191
4192/******************* Bit definition for CAN_F13R1 register ******************/
4193#define CAN_F13R1_FB0_Pos (0U)
4194#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
4195#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
4196#define CAN_F13R1_FB1_Pos (1U)
4197#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
4198#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
4199#define CAN_F13R1_FB2_Pos (2U)
4200#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
4201#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
4202#define CAN_F13R1_FB3_Pos (3U)
4203#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
4204#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
4205#define CAN_F13R1_FB4_Pos (4U)
4206#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
4207#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
4208#define CAN_F13R1_FB5_Pos (5U)
4209#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
4210#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
4211#define CAN_F13R1_FB6_Pos (6U)
4212#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
4213#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
4214#define CAN_F13R1_FB7_Pos (7U)
4215#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
4216#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
4217#define CAN_F13R1_FB8_Pos (8U)
4218#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
4219#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
4220#define CAN_F13R1_FB9_Pos (9U)
4221#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
4222#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
4223#define CAN_F13R1_FB10_Pos (10U)
4224#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
4225#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
4226#define CAN_F13R1_FB11_Pos (11U)
4227#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
4228#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
4229#define CAN_F13R1_FB12_Pos (12U)
4230#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
4231#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
4232#define CAN_F13R1_FB13_Pos (13U)
4233#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
4234#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
4235#define CAN_F13R1_FB14_Pos (14U)
4236#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
4237#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
4238#define CAN_F13R1_FB15_Pos (15U)
4239#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
4240#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
4241#define CAN_F13R1_FB16_Pos (16U)
4242#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
4243#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
4244#define CAN_F13R1_FB17_Pos (17U)
4245#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
4246#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
4247#define CAN_F13R1_FB18_Pos (18U)
4248#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
4249#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
4250#define CAN_F13R1_FB19_Pos (19U)
4251#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
4252#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
4253#define CAN_F13R1_FB20_Pos (20U)
4254#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
4255#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
4256#define CAN_F13R1_FB21_Pos (21U)
4257#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
4258#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
4259#define CAN_F13R1_FB22_Pos (22U)
4260#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
4261#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
4262#define CAN_F13R1_FB23_Pos (23U)
4263#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
4264#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
4265#define CAN_F13R1_FB24_Pos (24U)
4266#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
4267#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
4268#define CAN_F13R1_FB25_Pos (25U)
4269#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
4270#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
4271#define CAN_F13R1_FB26_Pos (26U)
4272#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
4273#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
4274#define CAN_F13R1_FB27_Pos (27U)
4275#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
4276#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
4277#define CAN_F13R1_FB28_Pos (28U)
4278#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
4279#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
4280#define CAN_F13R1_FB29_Pos (29U)
4281#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
4282#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
4283#define CAN_F13R1_FB30_Pos (30U)
4284#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
4285#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
4286#define CAN_F13R1_FB31_Pos (31U)
4287#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
4288#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
4289
4290/******************* Bit definition for CAN_F0R2 register *******************/
4291#define CAN_F0R2_FB0_Pos (0U)
4292#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
4293#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
4294#define CAN_F0R2_FB1_Pos (1U)
4295#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
4296#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
4297#define CAN_F0R2_FB2_Pos (2U)
4298#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
4299#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
4300#define CAN_F0R2_FB3_Pos (3U)
4301#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
4302#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
4303#define CAN_F0R2_FB4_Pos (4U)
4304#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
4305#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
4306#define CAN_F0R2_FB5_Pos (5U)
4307#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
4308#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
4309#define CAN_F0R2_FB6_Pos (6U)
4310#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
4311#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
4312#define CAN_F0R2_FB7_Pos (7U)
4313#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
4314#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
4315#define CAN_F0R2_FB8_Pos (8U)
4316#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
4317#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
4318#define CAN_F0R2_FB9_Pos (9U)
4319#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
4320#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
4321#define CAN_F0R2_FB10_Pos (10U)
4322#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
4323#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
4324#define CAN_F0R2_FB11_Pos (11U)
4325#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
4326#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
4327#define CAN_F0R2_FB12_Pos (12U)
4328#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
4329#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
4330#define CAN_F0R2_FB13_Pos (13U)
4331#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
4332#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
4333#define CAN_F0R2_FB14_Pos (14U)
4334#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
4335#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
4336#define CAN_F0R2_FB15_Pos (15U)
4337#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
4338#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
4339#define CAN_F0R2_FB16_Pos (16U)
4340#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
4341#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
4342#define CAN_F0R2_FB17_Pos (17U)
4343#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
4344#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
4345#define CAN_F0R2_FB18_Pos (18U)
4346#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
4347#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
4348#define CAN_F0R2_FB19_Pos (19U)
4349#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
4350#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
4351#define CAN_F0R2_FB20_Pos (20U)
4352#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
4353#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
4354#define CAN_F0R2_FB21_Pos (21U)
4355#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
4356#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
4357#define CAN_F0R2_FB22_Pos (22U)
4358#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
4359#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
4360#define CAN_F0R2_FB23_Pos (23U)
4361#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
4362#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
4363#define CAN_F0R2_FB24_Pos (24U)
4364#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
4365#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
4366#define CAN_F0R2_FB25_Pos (25U)
4367#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
4368#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
4369#define CAN_F0R2_FB26_Pos (26U)
4370#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
4371#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
4372#define CAN_F0R2_FB27_Pos (27U)
4373#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
4374#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
4375#define CAN_F0R2_FB28_Pos (28U)
4376#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
4377#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
4378#define CAN_F0R2_FB29_Pos (29U)
4379#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
4380#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
4381#define CAN_F0R2_FB30_Pos (30U)
4382#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
4383#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
4384#define CAN_F0R2_FB31_Pos (31U)
4385#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
4386#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
4387
4388/******************* Bit definition for CAN_F1R2 register *******************/
4389#define CAN_F1R2_FB0_Pos (0U)
4390#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
4391#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
4392#define CAN_F1R2_FB1_Pos (1U)
4393#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
4394#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
4395#define CAN_F1R2_FB2_Pos (2U)
4396#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
4397#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
4398#define CAN_F1R2_FB3_Pos (3U)
4399#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
4400#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
4401#define CAN_F1R2_FB4_Pos (4U)
4402#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
4403#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
4404#define CAN_F1R2_FB5_Pos (5U)
4405#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
4406#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
4407#define CAN_F1R2_FB6_Pos (6U)
4408#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
4409#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
4410#define CAN_F1R2_FB7_Pos (7U)
4411#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
4412#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
4413#define CAN_F1R2_FB8_Pos (8U)
4414#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
4415#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4416#define CAN_F1R2_FB9_Pos (9U)
4417#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4418#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4419#define CAN_F1R2_FB10_Pos (10U)
4420#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4421#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4422#define CAN_F1R2_FB11_Pos (11U)
4423#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4424#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4425#define CAN_F1R2_FB12_Pos (12U)
4426#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4427#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4428#define CAN_F1R2_FB13_Pos (13U)
4429#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4430#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4431#define CAN_F1R2_FB14_Pos (14U)
4432#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4433#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4434#define CAN_F1R2_FB15_Pos (15U)
4435#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4436#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4437#define CAN_F1R2_FB16_Pos (16U)
4438#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4439#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4440#define CAN_F1R2_FB17_Pos (17U)
4441#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4442#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4443#define CAN_F1R2_FB18_Pos (18U)
4444#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4445#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4446#define CAN_F1R2_FB19_Pos (19U)
4447#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4448#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4449#define CAN_F1R2_FB20_Pos (20U)
4450#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4451#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4452#define CAN_F1R2_FB21_Pos (21U)
4453#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4454#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4455#define CAN_F1R2_FB22_Pos (22U)
4456#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4457#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4458#define CAN_F1R2_FB23_Pos (23U)
4459#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4460#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4461#define CAN_F1R2_FB24_Pos (24U)
4462#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4463#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4464#define CAN_F1R2_FB25_Pos (25U)
4465#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4466#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4467#define CAN_F1R2_FB26_Pos (26U)
4468#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4469#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4470#define CAN_F1R2_FB27_Pos (27U)
4471#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4472#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4473#define CAN_F1R2_FB28_Pos (28U)
4474#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4475#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4476#define CAN_F1R2_FB29_Pos (29U)
4477#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4478#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4479#define CAN_F1R2_FB30_Pos (30U)
4480#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4481#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4482#define CAN_F1R2_FB31_Pos (31U)
4483#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4484#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4485
4486/******************* Bit definition for CAN_F2R2 register *******************/
4487#define CAN_F2R2_FB0_Pos (0U)
4488#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4489#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4490#define CAN_F2R2_FB1_Pos (1U)
4491#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4492#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4493#define CAN_F2R2_FB2_Pos (2U)
4494#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4495#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4496#define CAN_F2R2_FB3_Pos (3U)
4497#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4498#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4499#define CAN_F2R2_FB4_Pos (4U)
4500#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4501#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4502#define CAN_F2R2_FB5_Pos (5U)
4503#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4504#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4505#define CAN_F2R2_FB6_Pos (6U)
4506#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4507#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4508#define CAN_F2R2_FB7_Pos (7U)
4509#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4510#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4511#define CAN_F2R2_FB8_Pos (8U)
4512#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4513#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4514#define CAN_F2R2_FB9_Pos (9U)
4515#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4516#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4517#define CAN_F2R2_FB10_Pos (10U)
4518#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4519#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4520#define CAN_F2R2_FB11_Pos (11U)
4521#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4522#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4523#define CAN_F2R2_FB12_Pos (12U)
4524#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4525#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4526#define CAN_F2R2_FB13_Pos (13U)
4527#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4528#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4529#define CAN_F2R2_FB14_Pos (14U)
4530#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4531#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4532#define CAN_F2R2_FB15_Pos (15U)
4533#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4534#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4535#define CAN_F2R2_FB16_Pos (16U)
4536#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4537#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4538#define CAN_F2R2_FB17_Pos (17U)
4539#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4540#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4541#define CAN_F2R2_FB18_Pos (18U)
4542#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4543#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4544#define CAN_F2R2_FB19_Pos (19U)
4545#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4546#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4547#define CAN_F2R2_FB20_Pos (20U)
4548#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4549#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4550#define CAN_F2R2_FB21_Pos (21U)
4551#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4552#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4553#define CAN_F2R2_FB22_Pos (22U)
4554#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4555#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4556#define CAN_F2R2_FB23_Pos (23U)
4557#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4558#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4559#define CAN_F2R2_FB24_Pos (24U)
4560#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4561#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4562#define CAN_F2R2_FB25_Pos (25U)
4563#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4564#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4565#define CAN_F2R2_FB26_Pos (26U)
4566#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4567#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4568#define CAN_F2R2_FB27_Pos (27U)
4569#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4570#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4571#define CAN_F2R2_FB28_Pos (28U)
4572#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4573#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4574#define CAN_F2R2_FB29_Pos (29U)
4575#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4576#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4577#define CAN_F2R2_FB30_Pos (30U)
4578#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4579#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4580#define CAN_F2R2_FB31_Pos (31U)
4581#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4582#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4583
4584/******************* Bit definition for CAN_F3R2 register *******************/
4585#define CAN_F3R2_FB0_Pos (0U)
4586#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4587#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4588#define CAN_F3R2_FB1_Pos (1U)
4589#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4590#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4591#define CAN_F3R2_FB2_Pos (2U)
4592#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4593#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4594#define CAN_F3R2_FB3_Pos (3U)
4595#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4596#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4597#define CAN_F3R2_FB4_Pos (4U)
4598#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4599#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4600#define CAN_F3R2_FB5_Pos (5U)
4601#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4602#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4603#define CAN_F3R2_FB6_Pos (6U)
4604#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4605#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4606#define CAN_F3R2_FB7_Pos (7U)
4607#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4608#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4609#define CAN_F3R2_FB8_Pos (8U)
4610#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4611#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4612#define CAN_F3R2_FB9_Pos (9U)
4613#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4614#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4615#define CAN_F3R2_FB10_Pos (10U)
4616#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4617#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4618#define CAN_F3R2_FB11_Pos (11U)
4619#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4620#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4621#define CAN_F3R2_FB12_Pos (12U)
4622#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4623#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4624#define CAN_F3R2_FB13_Pos (13U)
4625#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4626#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4627#define CAN_F3R2_FB14_Pos (14U)
4628#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4629#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4630#define CAN_F3R2_FB15_Pos (15U)
4631#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4632#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4633#define CAN_F3R2_FB16_Pos (16U)
4634#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4635#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4636#define CAN_F3R2_FB17_Pos (17U)
4637#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4638#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4639#define CAN_F3R2_FB18_Pos (18U)
4640#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4641#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4642#define CAN_F3R2_FB19_Pos (19U)
4643#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4644#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4645#define CAN_F3R2_FB20_Pos (20U)
4646#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4647#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4648#define CAN_F3R2_FB21_Pos (21U)
4649#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4650#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4651#define CAN_F3R2_FB22_Pos (22U)
4652#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4653#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4654#define CAN_F3R2_FB23_Pos (23U)
4655#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4656#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4657#define CAN_F3R2_FB24_Pos (24U)
4658#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4659#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4660#define CAN_F3R2_FB25_Pos (25U)
4661#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4662#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4663#define CAN_F3R2_FB26_Pos (26U)
4664#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4665#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4666#define CAN_F3R2_FB27_Pos (27U)
4667#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4668#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4669#define CAN_F3R2_FB28_Pos (28U)
4670#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4671#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4672#define CAN_F3R2_FB29_Pos (29U)
4673#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4674#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4675#define CAN_F3R2_FB30_Pos (30U)
4676#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4677#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4678#define CAN_F3R2_FB31_Pos (31U)
4679#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4680#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4681
4682/******************* Bit definition for CAN_F4R2 register *******************/
4683#define CAN_F4R2_FB0_Pos (0U)
4684#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4685#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4686#define CAN_F4R2_FB1_Pos (1U)
4687#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4688#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4689#define CAN_F4R2_FB2_Pos (2U)
4690#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4691#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4692#define CAN_F4R2_FB3_Pos (3U)
4693#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4694#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4695#define CAN_F4R2_FB4_Pos (4U)
4696#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4697#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4698#define CAN_F4R2_FB5_Pos (5U)
4699#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4700#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4701#define CAN_F4R2_FB6_Pos (6U)
4702#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4703#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4704#define CAN_F4R2_FB7_Pos (7U)
4705#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4706#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4707#define CAN_F4R2_FB8_Pos (8U)
4708#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4709#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4710#define CAN_F4R2_FB9_Pos (9U)
4711#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4712#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4713#define CAN_F4R2_FB10_Pos (10U)
4714#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4715#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4716#define CAN_F4R2_FB11_Pos (11U)
4717#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4718#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4719#define CAN_F4R2_FB12_Pos (12U)
4720#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4721#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4722#define CAN_F4R2_FB13_Pos (13U)
4723#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4724#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4725#define CAN_F4R2_FB14_Pos (14U)
4726#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4727#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4728#define CAN_F4R2_FB15_Pos (15U)
4729#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4730#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4731#define CAN_F4R2_FB16_Pos (16U)
4732#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4733#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4734#define CAN_F4R2_FB17_Pos (17U)
4735#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4736#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4737#define CAN_F4R2_FB18_Pos (18U)
4738#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4739#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4740#define CAN_F4R2_FB19_Pos (19U)
4741#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4742#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4743#define CAN_F4R2_FB20_Pos (20U)
4744#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4745#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4746#define CAN_F4R2_FB21_Pos (21U)
4747#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4748#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4749#define CAN_F4R2_FB22_Pos (22U)
4750#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4751#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4752#define CAN_F4R2_FB23_Pos (23U)
4753#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4754#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4755#define CAN_F4R2_FB24_Pos (24U)
4756#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4757#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4758#define CAN_F4R2_FB25_Pos (25U)
4759#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4760#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4761#define CAN_F4R2_FB26_Pos (26U)
4762#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4763#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4764#define CAN_F4R2_FB27_Pos (27U)
4765#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4766#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4767#define CAN_F4R2_FB28_Pos (28U)
4768#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4769#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4770#define CAN_F4R2_FB29_Pos (29U)
4771#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4772#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4773#define CAN_F4R2_FB30_Pos (30U)
4774#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4775#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4776#define CAN_F4R2_FB31_Pos (31U)
4777#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4778#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4779
4780/******************* Bit definition for CAN_F5R2 register *******************/
4781#define CAN_F5R2_FB0_Pos (0U)
4782#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4783#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4784#define CAN_F5R2_FB1_Pos (1U)
4785#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4786#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4787#define CAN_F5R2_FB2_Pos (2U)
4788#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4789#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4790#define CAN_F5R2_FB3_Pos (3U)
4791#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4792#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4793#define CAN_F5R2_FB4_Pos (4U)
4794#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4795#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4796#define CAN_F5R2_FB5_Pos (5U)
4797#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4798#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4799#define CAN_F5R2_FB6_Pos (6U)
4800#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4801#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4802#define CAN_F5R2_FB7_Pos (7U)
4803#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4804#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4805#define CAN_F5R2_FB8_Pos (8U)
4806#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4807#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4808#define CAN_F5R2_FB9_Pos (9U)
4809#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4810#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4811#define CAN_F5R2_FB10_Pos (10U)
4812#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4813#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4814#define CAN_F5R2_FB11_Pos (11U)
4815#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4816#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4817#define CAN_F5R2_FB12_Pos (12U)
4818#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4819#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4820#define CAN_F5R2_FB13_Pos (13U)
4821#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4822#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4823#define CAN_F5R2_FB14_Pos (14U)
4824#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4825#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4826#define CAN_F5R2_FB15_Pos (15U)
4827#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4828#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4829#define CAN_F5R2_FB16_Pos (16U)
4830#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4831#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4832#define CAN_F5R2_FB17_Pos (17U)
4833#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4834#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4835#define CAN_F5R2_FB18_Pos (18U)
4836#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4837#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4838#define CAN_F5R2_FB19_Pos (19U)
4839#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4840#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4841#define CAN_F5R2_FB20_Pos (20U)
4842#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4843#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4844#define CAN_F5R2_FB21_Pos (21U)
4845#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4846#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4847#define CAN_F5R2_FB22_Pos (22U)
4848#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4849#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4850#define CAN_F5R2_FB23_Pos (23U)
4851#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4852#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4853#define CAN_F5R2_FB24_Pos (24U)
4854#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4855#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4856#define CAN_F5R2_FB25_Pos (25U)
4857#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4858#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4859#define CAN_F5R2_FB26_Pos (26U)
4860#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4861#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4862#define CAN_F5R2_FB27_Pos (27U)
4863#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4864#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4865#define CAN_F5R2_FB28_Pos (28U)
4866#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4867#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4868#define CAN_F5R2_FB29_Pos (29U)
4869#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4870#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4871#define CAN_F5R2_FB30_Pos (30U)
4872#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4873#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4874#define CAN_F5R2_FB31_Pos (31U)
4875#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4876#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4877
4878/******************* Bit definition for CAN_F6R2 register *******************/
4879#define CAN_F6R2_FB0_Pos (0U)
4880#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4881#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4882#define CAN_F6R2_FB1_Pos (1U)
4883#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4884#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4885#define CAN_F6R2_FB2_Pos (2U)
4886#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4887#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4888#define CAN_F6R2_FB3_Pos (3U)
4889#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4890#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4891#define CAN_F6R2_FB4_Pos (4U)
4892#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4893#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4894#define CAN_F6R2_FB5_Pos (5U)
4895#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4896#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4897#define CAN_F6R2_FB6_Pos (6U)
4898#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4899#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4900#define CAN_F6R2_FB7_Pos (7U)
4901#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4902#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4903#define CAN_F6R2_FB8_Pos (8U)
4904#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4905#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4906#define CAN_F6R2_FB9_Pos (9U)
4907#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4908#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4909#define CAN_F6R2_FB10_Pos (10U)
4910#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4911#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4912#define CAN_F6R2_FB11_Pos (11U)
4913#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4914#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4915#define CAN_F6R2_FB12_Pos (12U)
4916#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4917#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4918#define CAN_F6R2_FB13_Pos (13U)
4919#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4920#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4921#define CAN_F6R2_FB14_Pos (14U)
4922#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4923#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4924#define CAN_F6R2_FB15_Pos (15U)
4925#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4926#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4927#define CAN_F6R2_FB16_Pos (16U)
4928#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4929#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4930#define CAN_F6R2_FB17_Pos (17U)
4931#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4932#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4933#define CAN_F6R2_FB18_Pos (18U)
4934#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4935#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4936#define CAN_F6R2_FB19_Pos (19U)
4937#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4938#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4939#define CAN_F6R2_FB20_Pos (20U)
4940#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4941#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4942#define CAN_F6R2_FB21_Pos (21U)
4943#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4944#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4945#define CAN_F6R2_FB22_Pos (22U)
4946#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4947#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4948#define CAN_F6R2_FB23_Pos (23U)
4949#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4950#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4951#define CAN_F6R2_FB24_Pos (24U)
4952#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4953#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4954#define CAN_F6R2_FB25_Pos (25U)
4955#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4956#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4957#define CAN_F6R2_FB26_Pos (26U)
4958#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4959#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4960#define CAN_F6R2_FB27_Pos (27U)
4961#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4962#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4963#define CAN_F6R2_FB28_Pos (28U)
4964#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4965#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4966#define CAN_F6R2_FB29_Pos (29U)
4967#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4968#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4969#define CAN_F6R2_FB30_Pos (30U)
4970#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4971#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4972#define CAN_F6R2_FB31_Pos (31U)
4973#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4974#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4975
4976/******************* Bit definition for CAN_F7R2 register *******************/
4977#define CAN_F7R2_FB0_Pos (0U)
4978#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4979#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4980#define CAN_F7R2_FB1_Pos (1U)
4981#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4982#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4983#define CAN_F7R2_FB2_Pos (2U)
4984#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4985#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4986#define CAN_F7R2_FB3_Pos (3U)
4987#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4988#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4989#define CAN_F7R2_FB4_Pos (4U)
4990#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4991#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4992#define CAN_F7R2_FB5_Pos (5U)
4993#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4994#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4995#define CAN_F7R2_FB6_Pos (6U)
4996#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4997#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4998#define CAN_F7R2_FB7_Pos (7U)
4999#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
5000#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
5001#define CAN_F7R2_FB8_Pos (8U)
5002#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
5003#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
5004#define CAN_F7R2_FB9_Pos (9U)
5005#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
5006#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
5007#define CAN_F7R2_FB10_Pos (10U)
5008#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
5009#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
5010#define CAN_F7R2_FB11_Pos (11U)
5011#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
5012#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
5013#define CAN_F7R2_FB12_Pos (12U)
5014#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
5015#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
5016#define CAN_F7R2_FB13_Pos (13U)
5017#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
5018#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
5019#define CAN_F7R2_FB14_Pos (14U)
5020#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
5021#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
5022#define CAN_F7R2_FB15_Pos (15U)
5023#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
5024#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
5025#define CAN_F7R2_FB16_Pos (16U)
5026#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
5027#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
5028#define CAN_F7R2_FB17_Pos (17U)
5029#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
5030#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
5031#define CAN_F7R2_FB18_Pos (18U)
5032#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
5033#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
5034#define CAN_F7R2_FB19_Pos (19U)
5035#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
5036#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
5037#define CAN_F7R2_FB20_Pos (20U)
5038#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
5039#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
5040#define CAN_F7R2_FB21_Pos (21U)
5041#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
5042#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
5043#define CAN_F7R2_FB22_Pos (22U)
5044#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
5045#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
5046#define CAN_F7R2_FB23_Pos (23U)
5047#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
5048#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
5049#define CAN_F7R2_FB24_Pos (24U)
5050#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
5051#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
5052#define CAN_F7R2_FB25_Pos (25U)
5053#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
5054#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
5055#define CAN_F7R2_FB26_Pos (26U)
5056#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
5057#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
5058#define CAN_F7R2_FB27_Pos (27U)
5059#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
5060#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
5061#define CAN_F7R2_FB28_Pos (28U)
5062#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
5063#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
5064#define CAN_F7R2_FB29_Pos (29U)
5065#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
5066#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
5067#define CAN_F7R2_FB30_Pos (30U)
5068#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
5069#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
5070#define CAN_F7R2_FB31_Pos (31U)
5071#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
5072#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
5073
5074/******************* Bit definition for CAN_F8R2 register *******************/
5075#define CAN_F8R2_FB0_Pos (0U)
5076#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
5077#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
5078#define CAN_F8R2_FB1_Pos (1U)
5079#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
5080#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
5081#define CAN_F8R2_FB2_Pos (2U)
5082#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
5083#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
5084#define CAN_F8R2_FB3_Pos (3U)
5085#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
5086#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
5087#define CAN_F8R2_FB4_Pos (4U)
5088#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
5089#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
5090#define CAN_F8R2_FB5_Pos (5U)
5091#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
5092#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
5093#define CAN_F8R2_FB6_Pos (6U)
5094#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
5095#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
5096#define CAN_F8R2_FB7_Pos (7U)
5097#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
5098#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
5099#define CAN_F8R2_FB8_Pos (8U)
5100#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
5101#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
5102#define CAN_F8R2_FB9_Pos (9U)
5103#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
5104#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
5105#define CAN_F8R2_FB10_Pos (10U)
5106#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
5107#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
5108#define CAN_F8R2_FB11_Pos (11U)
5109#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
5110#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
5111#define CAN_F8R2_FB12_Pos (12U)
5112#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
5113#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
5114#define CAN_F8R2_FB13_Pos (13U)
5115#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
5116#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
5117#define CAN_F8R2_FB14_Pos (14U)
5118#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
5119#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
5120#define CAN_F8R2_FB15_Pos (15U)
5121#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
5122#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
5123#define CAN_F8R2_FB16_Pos (16U)
5124#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
5125#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
5126#define CAN_F8R2_FB17_Pos (17U)
5127#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
5128#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
5129#define CAN_F8R2_FB18_Pos (18U)
5130#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
5131#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
5132#define CAN_F8R2_FB19_Pos (19U)
5133#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
5134#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
5135#define CAN_F8R2_FB20_Pos (20U)
5136#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
5137#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
5138#define CAN_F8R2_FB21_Pos (21U)
5139#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
5140#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
5141#define CAN_F8R2_FB22_Pos (22U)
5142#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
5143#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
5144#define CAN_F8R2_FB23_Pos (23U)
5145#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
5146#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
5147#define CAN_F8R2_FB24_Pos (24U)
5148#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
5149#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
5150#define CAN_F8R2_FB25_Pos (25U)
5151#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
5152#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
5153#define CAN_F8R2_FB26_Pos (26U)
5154#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
5155#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
5156#define CAN_F8R2_FB27_Pos (27U)
5157#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
5158#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
5159#define CAN_F8R2_FB28_Pos (28U)
5160#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
5161#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
5162#define CAN_F8R2_FB29_Pos (29U)
5163#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
5164#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
5165#define CAN_F8R2_FB30_Pos (30U)
5166#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
5167#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
5168#define CAN_F8R2_FB31_Pos (31U)
5169#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
5170#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
5171
5172/******************* Bit definition for CAN_F9R2 register *******************/
5173#define CAN_F9R2_FB0_Pos (0U)
5174#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
5175#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
5176#define CAN_F9R2_FB1_Pos (1U)
5177#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
5178#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
5179#define CAN_F9R2_FB2_Pos (2U)
5180#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
5181#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
5182#define CAN_F9R2_FB3_Pos (3U)
5183#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
5184#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
5185#define CAN_F9R2_FB4_Pos (4U)
5186#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
5187#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
5188#define CAN_F9R2_FB5_Pos (5U)
5189#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
5190#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
5191#define CAN_F9R2_FB6_Pos (6U)
5192#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
5193#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
5194#define CAN_F9R2_FB7_Pos (7U)
5195#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
5196#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
5197#define CAN_F9R2_FB8_Pos (8U)
5198#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
5199#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
5200#define CAN_F9R2_FB9_Pos (9U)
5201#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
5202#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
5203#define CAN_F9R2_FB10_Pos (10U)
5204#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
5205#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
5206#define CAN_F9R2_FB11_Pos (11U)
5207#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
5208#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
5209#define CAN_F9R2_FB12_Pos (12U)
5210#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
5211#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
5212#define CAN_F9R2_FB13_Pos (13U)
5213#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
5214#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
5215#define CAN_F9R2_FB14_Pos (14U)
5216#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
5217#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
5218#define CAN_F9R2_FB15_Pos (15U)
5219#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
5220#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
5221#define CAN_F9R2_FB16_Pos (16U)
5222#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
5223#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
5224#define CAN_F9R2_FB17_Pos (17U)
5225#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
5226#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
5227#define CAN_F9R2_FB18_Pos (18U)
5228#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
5229#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
5230#define CAN_F9R2_FB19_Pos (19U)
5231#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
5232#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
5233#define CAN_F9R2_FB20_Pos (20U)
5234#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
5235#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
5236#define CAN_F9R2_FB21_Pos (21U)
5237#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
5238#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
5239#define CAN_F9R2_FB22_Pos (22U)
5240#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
5241#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
5242#define CAN_F9R2_FB23_Pos (23U)
5243#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
5244#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
5245#define CAN_F9R2_FB24_Pos (24U)
5246#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
5247#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
5248#define CAN_F9R2_FB25_Pos (25U)
5249#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
5250#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
5251#define CAN_F9R2_FB26_Pos (26U)
5252#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
5253#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
5254#define CAN_F9R2_FB27_Pos (27U)
5255#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
5256#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
5257#define CAN_F9R2_FB28_Pos (28U)
5258#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
5259#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
5260#define CAN_F9R2_FB29_Pos (29U)
5261#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
5262#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
5263#define CAN_F9R2_FB30_Pos (30U)
5264#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
5265#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
5266#define CAN_F9R2_FB31_Pos (31U)
5267#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
5268#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
5269
5270/******************* Bit definition for CAN_F10R2 register ******************/
5271#define CAN_F10R2_FB0_Pos (0U)
5272#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
5273#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
5274#define CAN_F10R2_FB1_Pos (1U)
5275#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
5276#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
5277#define CAN_F10R2_FB2_Pos (2U)
5278#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
5279#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
5280#define CAN_F10R2_FB3_Pos (3U)
5281#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
5282#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
5283#define CAN_F10R2_FB4_Pos (4U)
5284#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
5285#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
5286#define CAN_F10R2_FB5_Pos (5U)
5287#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
5288#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
5289#define CAN_F10R2_FB6_Pos (6U)
5290#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
5291#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
5292#define CAN_F10R2_FB7_Pos (7U)
5293#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
5294#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
5295#define CAN_F10R2_FB8_Pos (8U)
5296#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
5297#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
5298#define CAN_F10R2_FB9_Pos (9U)
5299#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
5300#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
5301#define CAN_F10R2_FB10_Pos (10U)
5302#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
5303#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
5304#define CAN_F10R2_FB11_Pos (11U)
5305#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
5306#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
5307#define CAN_F10R2_FB12_Pos (12U)
5308#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
5309#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
5310#define CAN_F10R2_FB13_Pos (13U)
5311#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
5312#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
5313#define CAN_F10R2_FB14_Pos (14U)
5314#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
5315#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
5316#define CAN_F10R2_FB15_Pos (15U)
5317#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
5318#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
5319#define CAN_F10R2_FB16_Pos (16U)
5320#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
5321#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
5322#define CAN_F10R2_FB17_Pos (17U)
5323#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
5324#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
5325#define CAN_F10R2_FB18_Pos (18U)
5326#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
5327#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
5328#define CAN_F10R2_FB19_Pos (19U)
5329#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
5330#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
5331#define CAN_F10R2_FB20_Pos (20U)
5332#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
5333#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
5334#define CAN_F10R2_FB21_Pos (21U)
5335#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
5336#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
5337#define CAN_F10R2_FB22_Pos (22U)
5338#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
5339#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
5340#define CAN_F10R2_FB23_Pos (23U)
5341#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
5342#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
5343#define CAN_F10R2_FB24_Pos (24U)
5344#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
5345#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
5346#define CAN_F10R2_FB25_Pos (25U)
5347#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
5348#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
5349#define CAN_F10R2_FB26_Pos (26U)
5350#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
5351#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
5352#define CAN_F10R2_FB27_Pos (27U)
5353#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
5354#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
5355#define CAN_F10R2_FB28_Pos (28U)
5356#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
5357#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
5358#define CAN_F10R2_FB29_Pos (29U)
5359#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
5360#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
5361#define CAN_F10R2_FB30_Pos (30U)
5362#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
5363#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
5364#define CAN_F10R2_FB31_Pos (31U)
5365#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
5366#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
5367
5368/******************* Bit definition for CAN_F11R2 register ******************/
5369#define CAN_F11R2_FB0_Pos (0U)
5370#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
5371#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
5372#define CAN_F11R2_FB1_Pos (1U)
5373#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
5374#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
5375#define CAN_F11R2_FB2_Pos (2U)
5376#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
5377#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
5378#define CAN_F11R2_FB3_Pos (3U)
5379#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
5380#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
5381#define CAN_F11R2_FB4_Pos (4U)
5382#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
5383#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
5384#define CAN_F11R2_FB5_Pos (5U)
5385#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
5386#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
5387#define CAN_F11R2_FB6_Pos (6U)
5388#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
5389#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
5390#define CAN_F11R2_FB7_Pos (7U)
5391#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
5392#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
5393#define CAN_F11R2_FB8_Pos (8U)
5394#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
5395#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
5396#define CAN_F11R2_FB9_Pos (9U)
5397#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
5398#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
5399#define CAN_F11R2_FB10_Pos (10U)
5400#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
5401#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
5402#define CAN_F11R2_FB11_Pos (11U)
5403#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
5404#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
5405#define CAN_F11R2_FB12_Pos (12U)
5406#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
5407#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
5408#define CAN_F11R2_FB13_Pos (13U)
5409#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
5410#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
5411#define CAN_F11R2_FB14_Pos (14U)
5412#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
5413#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
5414#define CAN_F11R2_FB15_Pos (15U)
5415#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5416#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5417#define CAN_F11R2_FB16_Pos (16U)
5418#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5419#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5420#define CAN_F11R2_FB17_Pos (17U)
5421#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5422#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5423#define CAN_F11R2_FB18_Pos (18U)
5424#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5425#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5426#define CAN_F11R2_FB19_Pos (19U)
5427#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5428#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5429#define CAN_F11R2_FB20_Pos (20U)
5430#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5431#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5432#define CAN_F11R2_FB21_Pos (21U)
5433#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5434#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5435#define CAN_F11R2_FB22_Pos (22U)
5436#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5437#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5438#define CAN_F11R2_FB23_Pos (23U)
5439#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5440#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5441#define CAN_F11R2_FB24_Pos (24U)
5442#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5443#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5444#define CAN_F11R2_FB25_Pos (25U)
5445#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5446#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5447#define CAN_F11R2_FB26_Pos (26U)
5448#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5449#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5450#define CAN_F11R2_FB27_Pos (27U)
5451#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5452#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5453#define CAN_F11R2_FB28_Pos (28U)
5454#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5455#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5456#define CAN_F11R2_FB29_Pos (29U)
5457#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5458#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5459#define CAN_F11R2_FB30_Pos (30U)
5460#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5461#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5462#define CAN_F11R2_FB31_Pos (31U)
5463#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5464#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5465
5466/******************* Bit definition for CAN_F12R2 register ******************/
5467#define CAN_F12R2_FB0_Pos (0U)
5468#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5469#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5470#define CAN_F12R2_FB1_Pos (1U)
5471#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5472#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5473#define CAN_F12R2_FB2_Pos (2U)
5474#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5475#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5476#define CAN_F12R2_FB3_Pos (3U)
5477#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5478#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5479#define CAN_F12R2_FB4_Pos (4U)
5480#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5481#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5482#define CAN_F12R2_FB5_Pos (5U)
5483#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5484#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5485#define CAN_F12R2_FB6_Pos (6U)
5486#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5487#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5488#define CAN_F12R2_FB7_Pos (7U)
5489#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5490#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5491#define CAN_F12R2_FB8_Pos (8U)
5492#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5493#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5494#define CAN_F12R2_FB9_Pos (9U)
5495#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5496#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5497#define CAN_F12R2_FB10_Pos (10U)
5498#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5499#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5500#define CAN_F12R2_FB11_Pos (11U)
5501#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5502#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5503#define CAN_F12R2_FB12_Pos (12U)
5504#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5505#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5506#define CAN_F12R2_FB13_Pos (13U)
5507#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5508#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5509#define CAN_F12R2_FB14_Pos (14U)
5510#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5511#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5512#define CAN_F12R2_FB15_Pos (15U)
5513#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5514#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5515#define CAN_F12R2_FB16_Pos (16U)
5516#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5517#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5518#define CAN_F12R2_FB17_Pos (17U)
5519#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5520#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5521#define CAN_F12R2_FB18_Pos (18U)
5522#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5523#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5524#define CAN_F12R2_FB19_Pos (19U)
5525#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5526#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5527#define CAN_F12R2_FB20_Pos (20U)
5528#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5529#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5530#define CAN_F12R2_FB21_Pos (21U)
5531#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5532#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5533#define CAN_F12R2_FB22_Pos (22U)
5534#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5535#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5536#define CAN_F12R2_FB23_Pos (23U)
5537#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5538#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5539#define CAN_F12R2_FB24_Pos (24U)
5540#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5541#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5542#define CAN_F12R2_FB25_Pos (25U)
5543#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5544#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5545#define CAN_F12R2_FB26_Pos (26U)
5546#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5547#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5548#define CAN_F12R2_FB27_Pos (27U)
5549#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5550#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5551#define CAN_F12R2_FB28_Pos (28U)
5552#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5553#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5554#define CAN_F12R2_FB29_Pos (29U)
5555#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5556#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5557#define CAN_F12R2_FB30_Pos (30U)
5558#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5559#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5560#define CAN_F12R2_FB31_Pos (31U)
5561#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5562#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5563
5564/******************* Bit definition for CAN_F13R2 register ******************/
5565#define CAN_F13R2_FB0_Pos (0U)
5566#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5567#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5568#define CAN_F13R2_FB1_Pos (1U)
5569#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5570#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5571#define CAN_F13R2_FB2_Pos (2U)
5572#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5573#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5574#define CAN_F13R2_FB3_Pos (3U)
5575#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5576#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5577#define CAN_F13R2_FB4_Pos (4U)
5578#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5579#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5580#define CAN_F13R2_FB5_Pos (5U)
5581#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5582#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5583#define CAN_F13R2_FB6_Pos (6U)
5584#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5585#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5586#define CAN_F13R2_FB7_Pos (7U)
5587#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5588#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5589#define CAN_F13R2_FB8_Pos (8U)
5590#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5591#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5592#define CAN_F13R2_FB9_Pos (9U)
5593#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5594#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5595#define CAN_F13R2_FB10_Pos (10U)
5596#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5597#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5598#define CAN_F13R2_FB11_Pos (11U)
5599#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5600#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5601#define CAN_F13R2_FB12_Pos (12U)
5602#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5603#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5604#define CAN_F13R2_FB13_Pos (13U)
5605#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5606#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5607#define CAN_F13R2_FB14_Pos (14U)
5608#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5609#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5610#define CAN_F13R2_FB15_Pos (15U)
5611#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5612#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5613#define CAN_F13R2_FB16_Pos (16U)
5614#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5615#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5616#define CAN_F13R2_FB17_Pos (17U)
5617#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5618#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5619#define CAN_F13R2_FB18_Pos (18U)
5620#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5621#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5622#define CAN_F13R2_FB19_Pos (19U)
5623#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5624#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5625#define CAN_F13R2_FB20_Pos (20U)
5626#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5627#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5628#define CAN_F13R2_FB21_Pos (21U)
5629#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5630#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5631#define CAN_F13R2_FB22_Pos (22U)
5632#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5633#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5634#define CAN_F13R2_FB23_Pos (23U)
5635#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5636#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5637#define CAN_F13R2_FB24_Pos (24U)
5638#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5639#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5640#define CAN_F13R2_FB25_Pos (25U)
5641#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5642#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5643#define CAN_F13R2_FB26_Pos (26U)
5644#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5645#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5646#define CAN_F13R2_FB27_Pos (27U)
5647#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5648#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5649#define CAN_F13R2_FB28_Pos (28U)
5650#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5651#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5652#define CAN_F13R2_FB29_Pos (29U)
5653#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5654#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5655#define CAN_F13R2_FB30_Pos (30U)
5656#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5657#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5658#define CAN_F13R2_FB31_Pos (31U)
5659#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5660#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5661
5662/******************************************************************************/
5663/* */
5664/* CRC calculation unit */
5665/* */
5666/******************************************************************************/
5667/******************* Bit definition for CRC_DR register *********************/
5668#define CRC_DR_DR_Pos (0U)
5669#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5670#define CRC_DR_DR CRC_DR_DR_Msk
5671
5672
5673/******************* Bit definition for CRC_IDR register ********************/
5674#define CRC_IDR_IDR_Pos (0U)
5675#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5676#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5677
5678
5679/******************** Bit definition for CRC_CR register ********************/
5680#define CRC_CR_RESET_Pos (0U)
5681#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5682#define CRC_CR_RESET CRC_CR_RESET_Msk
5683
5684/******************************************************************************/
5685/* */
5686/* Digital to Analog Converter */
5687/* */
5688/******************************************************************************/
5689/*
5690 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
5691 */
5692#define DAC_CHANNEL2_SUPPORT
5693/******************** Bit definition for DAC_CR register ********************/
5694#define DAC_CR_EN1_Pos (0U)
5695#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5696#define DAC_CR_EN1 DAC_CR_EN1_Msk
5697#define DAC_CR_BOFF1_Pos (1U)
5698#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5699#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5700#define DAC_CR_TEN1_Pos (2U)
5701#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5702#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5703
5704#define DAC_CR_TSEL1_Pos (3U)
5705#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5706#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5707#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5708#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5709#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5710
5711#define DAC_CR_WAVE1_Pos (6U)
5712#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5713#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5714#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5715#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5716
5717#define DAC_CR_MAMP1_Pos (8U)
5718#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5719#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5720#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5721#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5722#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5723#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5724
5725#define DAC_CR_DMAEN1_Pos (12U)
5726#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5727#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5728#define DAC_CR_DMAUDRIE1_Pos (13U)
5729#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5730#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5731#define DAC_CR_EN2_Pos (16U)
5732#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5733#define DAC_CR_EN2 DAC_CR_EN2_Msk
5734#define DAC_CR_BOFF2_Pos (17U)
5735#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5736#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5737#define DAC_CR_TEN2_Pos (18U)
5738#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5739#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5740
5741#define DAC_CR_TSEL2_Pos (19U)
5742#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5743#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5744#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5745#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5746#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5747
5748#define DAC_CR_WAVE2_Pos (22U)
5749#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5750#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5751#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5752#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5753
5754#define DAC_CR_MAMP2_Pos (24U)
5755#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5756#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5757#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5758#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5759#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5760#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5761
5762#define DAC_CR_DMAEN2_Pos (28U)
5763#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5764#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5765#define DAC_CR_DMAUDRIE2_Pos (29U)
5766#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5767#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5768
5769/***************** Bit definition for DAC_SWTRIGR register ******************/
5770#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5771#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5772#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5773#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5774#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5775#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5776
5777/***************** Bit definition for DAC_DHR12R1 register ******************/
5778#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5779#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5780#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5781
5782/***************** Bit definition for DAC_DHR12L1 register ******************/
5783#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5784#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5785#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5786
5787/****************** Bit definition for DAC_DHR8R1 register ******************/
5788#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5789#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5790#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5791
5792/***************** Bit definition for DAC_DHR12R2 register ******************/
5793#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5794#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5795#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5796
5797/***************** Bit definition for DAC_DHR12L2 register ******************/
5798#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5799#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5800#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5801
5802/****************** Bit definition for DAC_DHR8R2 register ******************/
5803#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5804#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5805#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5806
5807/***************** Bit definition for DAC_DHR12RD register ******************/
5808#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5809#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5810#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5811#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5812#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5813#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5814
5815/***************** Bit definition for DAC_DHR12LD register ******************/
5816#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5817#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5818#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5819#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5820#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5821#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5822
5823/****************** Bit definition for DAC_DHR8RD register ******************/
5824#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5825#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5826#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5827#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5828#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5829#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5830
5831/******************* Bit definition for DAC_DOR1 register *******************/
5832#define DAC_DOR1_DACC1DOR_Pos (0U)
5833#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5834#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5835
5836/******************* Bit definition for DAC_DOR2 register *******************/
5837#define DAC_DOR2_DACC2DOR_Pos (0U)
5838#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5839#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5840
5841/******************** Bit definition for DAC_SR register ********************/
5842#define DAC_SR_DMAUDR1_Pos (13U)
5843#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5844#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5845#define DAC_SR_DMAUDR2_Pos (29U)
5846#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5847#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5848
5849/******************************************************************************/
5850/* */
5851/* DCMI */
5852/* */
5853/******************************************************************************/
5854/******************** Bits definition for DCMI_CR register ******************/
5855#define DCMI_CR_CAPTURE_Pos (0U)
5856#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5857#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5858#define DCMI_CR_CM_Pos (1U)
5859#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5860#define DCMI_CR_CM DCMI_CR_CM_Msk
5861#define DCMI_CR_CROP_Pos (2U)
5862#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5863#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5864#define DCMI_CR_JPEG_Pos (3U)
5865#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5866#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5867#define DCMI_CR_ESS_Pos (4U)
5868#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5869#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5870#define DCMI_CR_PCKPOL_Pos (5U)
5871#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5872#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5873#define DCMI_CR_HSPOL_Pos (6U)
5874#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5875#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5876#define DCMI_CR_VSPOL_Pos (7U)
5877#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5878#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5879#define DCMI_CR_FCRC_0 0x00000100U
5880#define DCMI_CR_FCRC_1 0x00000200U
5881#define DCMI_CR_EDM_0 0x00000400U
5882#define DCMI_CR_EDM_1 0x00000800U
5883#define DCMI_CR_OUTEN_Pos (13U)
5884#define DCMI_CR_OUTEN_Msk (0x1UL << DCMI_CR_OUTEN_Pos)
5885#define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
5886#define DCMI_CR_ENABLE_Pos (14U)
5887#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5888#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5889#define DCMI_CR_BSM_0 0x00010000U
5890#define DCMI_CR_BSM_1 0x00020000U
5891#define DCMI_CR_OEBS_Pos (18U)
5892#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
5893#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5894#define DCMI_CR_LSM_Pos (19U)
5895#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
5896#define DCMI_CR_LSM DCMI_CR_LSM_Msk
5897#define DCMI_CR_OELS_Pos (20U)
5898#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
5899#define DCMI_CR_OELS DCMI_CR_OELS_Msk
5900
5901/******************** Bits definition for DCMI_SR register ******************/
5902#define DCMI_SR_HSYNC_Pos (0U)
5903#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5904#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5905#define DCMI_SR_VSYNC_Pos (1U)
5906#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5907#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5908#define DCMI_SR_FNE_Pos (2U)
5909#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5910#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5911
5912/******************** Bits definition for DCMI_RIS register *****************/
5913#define DCMI_RIS_FRAME_RIS_Pos (0U)
5914#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5915#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5916#define DCMI_RIS_OVR_RIS_Pos (1U)
5917#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5918#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5919#define DCMI_RIS_ERR_RIS_Pos (2U)
5920#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5921#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5922#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5923#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5924#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5925#define DCMI_RIS_LINE_RIS_Pos (4U)
5926#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5927#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5928/* Legacy defines */
5929#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5930#define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5931#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5932#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5933#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5934#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5935
5936/******************** Bits definition for DCMI_IER register *****************/
5937#define DCMI_IER_FRAME_IE_Pos (0U)
5938#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5939#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5940#define DCMI_IER_OVR_IE_Pos (1U)
5941#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5942#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5943#define DCMI_IER_ERR_IE_Pos (2U)
5944#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5945#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5946#define DCMI_IER_VSYNC_IE_Pos (3U)
5947#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5948#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5949#define DCMI_IER_LINE_IE_Pos (4U)
5950#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5951#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5952/* Legacy defines */
5953#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5954
5955/******************** Bits definition for DCMI_MIS register *****************/
5956#define DCMI_MIS_FRAME_MIS_Pos (0U)
5957#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5958#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5959#define DCMI_MIS_OVR_MIS_Pos (1U)
5960#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5961#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5962#define DCMI_MIS_ERR_MIS_Pos (2U)
5963#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5964#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5965#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5966#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5967#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5968#define DCMI_MIS_LINE_MIS_Pos (4U)
5969#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5970#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5971
5972/* Legacy defines */
5973#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5974#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5975#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5976#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5977#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5978
5979/******************** Bits definition for DCMI_ICR register *****************/
5980#define DCMI_ICR_FRAME_ISC_Pos (0U)
5981#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5982#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5983#define DCMI_ICR_OVR_ISC_Pos (1U)
5984#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5985#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5986#define DCMI_ICR_ERR_ISC_Pos (2U)
5987#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5988#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5989#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5990#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5991#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5992#define DCMI_ICR_LINE_ISC_Pos (4U)
5993#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5994#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5995
5996/* Legacy defines */
5997#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
5998
5999/******************** Bits definition for DCMI_ESCR register ******************/
6000#define DCMI_ESCR_FSC_Pos (0U)
6001#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
6002#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6003#define DCMI_ESCR_LSC_Pos (8U)
6004#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6005#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6006#define DCMI_ESCR_LEC_Pos (16U)
6007#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6008#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6009#define DCMI_ESCR_FEC_Pos (24U)
6010#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6011#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6012
6013/******************** Bits definition for DCMI_ESUR register ******************/
6014#define DCMI_ESUR_FSU_Pos (0U)
6015#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6016#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6017#define DCMI_ESUR_LSU_Pos (8U)
6018#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6019#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6020#define DCMI_ESUR_LEU_Pos (16U)
6021#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6022#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6023#define DCMI_ESUR_FEU_Pos (24U)
6024#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6025#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6026
6027/******************** Bits definition for DCMI_CWSTRT register ******************/
6028#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6029#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6030#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6031#define DCMI_CWSTRT_VST_Pos (16U)
6032#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6033#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6034
6035/******************** Bits definition for DCMI_CWSIZE register ******************/
6036#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6037#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6038#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6039#define DCMI_CWSIZE_VLINE_Pos (16U)
6040#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6041#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6042
6043/******************** Bits definition for DCMI_DR register *********************/
6044#define DCMI_DR_BYTE0_Pos (0U)
6045#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6046#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6047#define DCMI_DR_BYTE1_Pos (8U)
6048#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6049#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6050#define DCMI_DR_BYTE2_Pos (16U)
6051#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6052#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6053#define DCMI_DR_BYTE3_Pos (24U)
6054#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6055#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6056
6057/******************************************************************************/
6058/* */
6059/* DMA Controller */
6060/* */
6061/******************************************************************************/
6062/******************** Bits definition for DMA_SxCR register *****************/
6063#define DMA_SxCR_CHSEL_Pos (25U)
6064#define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
6065#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6066#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
6067#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
6068#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
6069#define DMA_SxCR_MBURST_Pos (23U)
6070#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
6071#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6072#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
6073#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
6074#define DMA_SxCR_PBURST_Pos (21U)
6075#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
6076#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6077#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
6078#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
6079#define DMA_SxCR_CT_Pos (19U)
6080#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
6081#define DMA_SxCR_CT DMA_SxCR_CT_Msk
6082#define DMA_SxCR_DBM_Pos (18U)
6083#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
6084#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6085#define DMA_SxCR_PL_Pos (16U)
6086#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
6087#define DMA_SxCR_PL DMA_SxCR_PL_Msk
6088#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
6089#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
6090#define DMA_SxCR_PINCOS_Pos (15U)
6091#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
6092#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6093#define DMA_SxCR_MSIZE_Pos (13U)
6094#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
6095#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6096#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
6097#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
6098#define DMA_SxCR_PSIZE_Pos (11U)
6099#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
6100#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6101#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
6102#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
6103#define DMA_SxCR_MINC_Pos (10U)
6104#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
6105#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6106#define DMA_SxCR_PINC_Pos (9U)
6107#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
6108#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6109#define DMA_SxCR_CIRC_Pos (8U)
6110#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
6111#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6112#define DMA_SxCR_DIR_Pos (6U)
6113#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
6114#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6115#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
6116#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
6117#define DMA_SxCR_PFCTRL_Pos (5U)
6118#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
6119#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6120#define DMA_SxCR_TCIE_Pos (4U)
6121#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
6122#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6123#define DMA_SxCR_HTIE_Pos (3U)
6124#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
6125#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6126#define DMA_SxCR_TEIE_Pos (2U)
6127#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
6128#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6129#define DMA_SxCR_DMEIE_Pos (1U)
6130#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
6131#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6132#define DMA_SxCR_EN_Pos (0U)
6133#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
6134#define DMA_SxCR_EN DMA_SxCR_EN_Msk
6135
6136/* Legacy defines */
6137#define DMA_SxCR_ACK_Pos (20U)
6138#define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
6139#define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6140
6141/******************** Bits definition for DMA_SxCNDTR register **************/
6142#define DMA_SxNDT_Pos (0U)
6143#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
6144#define DMA_SxNDT DMA_SxNDT_Msk
6145#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
6146#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
6147#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
6148#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
6149#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
6150#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
6151#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
6152#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
6153#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
6154#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
6155#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
6156#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
6157#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
6158#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
6159#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
6160#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
6161
6162/******************** Bits definition for DMA_SxFCR register ****************/
6163#define DMA_SxFCR_FEIE_Pos (7U)
6164#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
6165#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6166#define DMA_SxFCR_FS_Pos (3U)
6167#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
6168#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6169#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
6170#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
6171#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
6172#define DMA_SxFCR_DMDIS_Pos (2U)
6173#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
6174#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6175#define DMA_SxFCR_FTH_Pos (0U)
6176#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
6177#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6178#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
6179#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
6180
6181/******************** Bits definition for DMA_LISR register *****************/
6182#define DMA_LISR_TCIF3_Pos (27U)
6183#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
6184#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6185#define DMA_LISR_HTIF3_Pos (26U)
6186#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
6187#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6188#define DMA_LISR_TEIF3_Pos (25U)
6189#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
6190#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6191#define DMA_LISR_DMEIF3_Pos (24U)
6192#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
6193#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6194#define DMA_LISR_FEIF3_Pos (22U)
6195#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
6196#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6197#define DMA_LISR_TCIF2_Pos (21U)
6198#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
6199#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6200#define DMA_LISR_HTIF2_Pos (20U)
6201#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
6202#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6203#define DMA_LISR_TEIF2_Pos (19U)
6204#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
6205#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6206#define DMA_LISR_DMEIF2_Pos (18U)
6207#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
6208#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6209#define DMA_LISR_FEIF2_Pos (16U)
6210#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
6211#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6212#define DMA_LISR_TCIF1_Pos (11U)
6213#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
6214#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6215#define DMA_LISR_HTIF1_Pos (10U)
6216#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
6217#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6218#define DMA_LISR_TEIF1_Pos (9U)
6219#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
6220#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6221#define DMA_LISR_DMEIF1_Pos (8U)
6222#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
6223#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6224#define DMA_LISR_FEIF1_Pos (6U)
6225#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
6226#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6227#define DMA_LISR_TCIF0_Pos (5U)
6228#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
6229#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6230#define DMA_LISR_HTIF0_Pos (4U)
6231#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
6232#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6233#define DMA_LISR_TEIF0_Pos (3U)
6234#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
6235#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6236#define DMA_LISR_DMEIF0_Pos (2U)
6237#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
6238#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6239#define DMA_LISR_FEIF0_Pos (0U)
6240#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
6241#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6242
6243/******************** Bits definition for DMA_HISR register *****************/
6244#define DMA_HISR_TCIF7_Pos (27U)
6245#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
6246#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6247#define DMA_HISR_HTIF7_Pos (26U)
6248#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
6249#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6250#define DMA_HISR_TEIF7_Pos (25U)
6251#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
6252#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6253#define DMA_HISR_DMEIF7_Pos (24U)
6254#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
6255#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6256#define DMA_HISR_FEIF7_Pos (22U)
6257#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
6258#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6259#define DMA_HISR_TCIF6_Pos (21U)
6260#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
6261#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6262#define DMA_HISR_HTIF6_Pos (20U)
6263#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
6264#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6265#define DMA_HISR_TEIF6_Pos (19U)
6266#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
6267#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6268#define DMA_HISR_DMEIF6_Pos (18U)
6269#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
6270#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6271#define DMA_HISR_FEIF6_Pos (16U)
6272#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
6273#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6274#define DMA_HISR_TCIF5_Pos (11U)
6275#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
6276#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6277#define DMA_HISR_HTIF5_Pos (10U)
6278#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
6279#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6280#define DMA_HISR_TEIF5_Pos (9U)
6281#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
6282#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6283#define DMA_HISR_DMEIF5_Pos (8U)
6284#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
6285#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6286#define DMA_HISR_FEIF5_Pos (6U)
6287#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
6288#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6289#define DMA_HISR_TCIF4_Pos (5U)
6290#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
6291#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6292#define DMA_HISR_HTIF4_Pos (4U)
6293#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
6294#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6295#define DMA_HISR_TEIF4_Pos (3U)
6296#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
6297#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6298#define DMA_HISR_DMEIF4_Pos (2U)
6299#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
6300#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6301#define DMA_HISR_FEIF4_Pos (0U)
6302#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
6303#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6304
6305/******************** Bits definition for DMA_LIFCR register ****************/
6306#define DMA_LIFCR_CTCIF3_Pos (27U)
6307#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
6308#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6309#define DMA_LIFCR_CHTIF3_Pos (26U)
6310#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
6311#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6312#define DMA_LIFCR_CTEIF3_Pos (25U)
6313#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
6314#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6315#define DMA_LIFCR_CDMEIF3_Pos (24U)
6316#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
6317#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6318#define DMA_LIFCR_CFEIF3_Pos (22U)
6319#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
6320#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6321#define DMA_LIFCR_CTCIF2_Pos (21U)
6322#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
6323#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6324#define DMA_LIFCR_CHTIF2_Pos (20U)
6325#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
6326#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6327#define DMA_LIFCR_CTEIF2_Pos (19U)
6328#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
6329#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6330#define DMA_LIFCR_CDMEIF2_Pos (18U)
6331#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
6332#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6333#define DMA_LIFCR_CFEIF2_Pos (16U)
6334#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
6335#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6336#define DMA_LIFCR_CTCIF1_Pos (11U)
6337#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
6338#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6339#define DMA_LIFCR_CHTIF1_Pos (10U)
6340#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
6341#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6342#define DMA_LIFCR_CTEIF1_Pos (9U)
6343#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
6344#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6345#define DMA_LIFCR_CDMEIF1_Pos (8U)
6346#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
6347#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6348#define DMA_LIFCR_CFEIF1_Pos (6U)
6349#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
6350#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6351#define DMA_LIFCR_CTCIF0_Pos (5U)
6352#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
6353#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6354#define DMA_LIFCR_CHTIF0_Pos (4U)
6355#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
6356#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6357#define DMA_LIFCR_CTEIF0_Pos (3U)
6358#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
6359#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6360#define DMA_LIFCR_CDMEIF0_Pos (2U)
6361#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
6362#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6363#define DMA_LIFCR_CFEIF0_Pos (0U)
6364#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
6365#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6366
6367/******************** Bits definition for DMA_HIFCR register ****************/
6368#define DMA_HIFCR_CTCIF7_Pos (27U)
6369#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
6370#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6371#define DMA_HIFCR_CHTIF7_Pos (26U)
6372#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
6373#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6374#define DMA_HIFCR_CTEIF7_Pos (25U)
6375#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
6376#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6377#define DMA_HIFCR_CDMEIF7_Pos (24U)
6378#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
6379#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6380#define DMA_HIFCR_CFEIF7_Pos (22U)
6381#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
6382#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6383#define DMA_HIFCR_CTCIF6_Pos (21U)
6384#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
6385#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6386#define DMA_HIFCR_CHTIF6_Pos (20U)
6387#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
6388#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6389#define DMA_HIFCR_CTEIF6_Pos (19U)
6390#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
6391#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6392#define DMA_HIFCR_CDMEIF6_Pos (18U)
6393#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
6394#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6395#define DMA_HIFCR_CFEIF6_Pos (16U)
6396#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
6397#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6398#define DMA_HIFCR_CTCIF5_Pos (11U)
6399#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
6400#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6401#define DMA_HIFCR_CHTIF5_Pos (10U)
6402#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
6403#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6404#define DMA_HIFCR_CTEIF5_Pos (9U)
6405#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
6406#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6407#define DMA_HIFCR_CDMEIF5_Pos (8U)
6408#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
6409#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6410#define DMA_HIFCR_CFEIF5_Pos (6U)
6411#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
6412#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6413#define DMA_HIFCR_CTCIF4_Pos (5U)
6414#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
6415#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6416#define DMA_HIFCR_CHTIF4_Pos (4U)
6417#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
6418#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6419#define DMA_HIFCR_CTEIF4_Pos (3U)
6420#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
6421#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6422#define DMA_HIFCR_CDMEIF4_Pos (2U)
6423#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
6424#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6425#define DMA_HIFCR_CFEIF4_Pos (0U)
6426#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
6427#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6428
6429/****************** Bit definition for DMA_SxPAR register ********************/
6430#define DMA_SxPAR_PA_Pos (0U)
6431#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
6432#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
6433
6434/****************** Bit definition for DMA_SxM0AR register ********************/
6435#define DMA_SxM0AR_M0A_Pos (0U)
6436#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
6437#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
6438
6439/****************** Bit definition for DMA_SxM1AR register ********************/
6440#define DMA_SxM1AR_M1A_Pos (0U)
6441#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
6442#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
6443
6444
6445/******************************************************************************/
6446/* */
6447/* AHB Master DMA2D Controller (DMA2D) */
6448/* */
6449/******************************************************************************/
6450
6451/******************** Bit definition for DMA2D_CR register ******************/
6452
6453#define DMA2D_CR_START_Pos (0U)
6454#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
6455#define DMA2D_CR_START DMA2D_CR_START_Msk
6456#define DMA2D_CR_SUSP_Pos (1U)
6457#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
6458#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
6459#define DMA2D_CR_ABORT_Pos (2U)
6460#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
6461#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
6462#define DMA2D_CR_TEIE_Pos (8U)
6463#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
6464#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
6465#define DMA2D_CR_TCIE_Pos (9U)
6466#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
6467#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
6468#define DMA2D_CR_TWIE_Pos (10U)
6469#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
6470#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
6471#define DMA2D_CR_CAEIE_Pos (11U)
6472#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
6473#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
6474#define DMA2D_CR_CTCIE_Pos (12U)
6475#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
6476#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
6477#define DMA2D_CR_CEIE_Pos (13U)
6478#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
6479#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
6480#define DMA2D_CR_MODE_Pos (16U)
6481#define DMA2D_CR_MODE_Msk (0x3UL << DMA2D_CR_MODE_Pos)
6482#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
6483#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
6484#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
6485
6486/******************** Bit definition for DMA2D_ISR register *****************/
6487
6488#define DMA2D_ISR_TEIF_Pos (0U)
6489#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
6490#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
6491#define DMA2D_ISR_TCIF_Pos (1U)
6492#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
6493#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
6494#define DMA2D_ISR_TWIF_Pos (2U)
6495#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
6496#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
6497#define DMA2D_ISR_CAEIF_Pos (3U)
6498#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
6499#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
6500#define DMA2D_ISR_CTCIF_Pos (4U)
6501#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
6502#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
6503#define DMA2D_ISR_CEIF_Pos (5U)
6504#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
6505#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
6506
6507/******************** Bit definition for DMA2D_IFCR register ****************/
6508
6509#define DMA2D_IFCR_CTEIF_Pos (0U)
6510#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
6511#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
6512#define DMA2D_IFCR_CTCIF_Pos (1U)
6513#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
6514#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
6515#define DMA2D_IFCR_CTWIF_Pos (2U)
6516#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
6517#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
6518#define DMA2D_IFCR_CAECIF_Pos (3U)
6519#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
6520#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
6521#define DMA2D_IFCR_CCTCIF_Pos (4U)
6522#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
6523#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
6524#define DMA2D_IFCR_CCEIF_Pos (5U)
6525#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
6526#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
6527
6528/* Legacy defines */
6529#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF
6530#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF
6531#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF
6532#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF
6533#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF
6534#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF
6535
6536/******************** Bit definition for DMA2D_FGMAR register ***************/
6537
6538#define DMA2D_FGMAR_MA_Pos (0U)
6539#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
6540#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
6541
6542/******************** Bit definition for DMA2D_FGOR register ****************/
6543
6544#define DMA2D_FGOR_LO_Pos (0U)
6545#define DMA2D_FGOR_LO_Msk (0x3FFFUL << DMA2D_FGOR_LO_Pos)
6546#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
6547
6548/******************** Bit definition for DMA2D_BGMAR register ***************/
6549
6550#define DMA2D_BGMAR_MA_Pos (0U)
6551#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
6552#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
6553
6554/******************** Bit definition for DMA2D_BGOR register ****************/
6555
6556#define DMA2D_BGOR_LO_Pos (0U)
6557#define DMA2D_BGOR_LO_Msk (0x3FFFUL << DMA2D_BGOR_LO_Pos)
6558#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
6559
6560/******************** Bit definition for DMA2D_FGPFCCR register *************/
6561
6562#define DMA2D_FGPFCCR_CM_Pos (0U)
6563#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
6564#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
6565#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
6566#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
6567#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
6568#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
6569#define DMA2D_FGPFCCR_CCM_Pos (4U)
6570#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
6571#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
6572#define DMA2D_FGPFCCR_START_Pos (5U)
6573#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
6574#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
6575#define DMA2D_FGPFCCR_CS_Pos (8U)
6576#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
6577#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
6578#define DMA2D_FGPFCCR_AM_Pos (16U)
6579#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
6580#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
6581#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
6582#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
6583#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6584#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
6585#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
6586
6587/******************** Bit definition for DMA2D_FGCOLR register **************/
6588
6589#define DMA2D_FGCOLR_BLUE_Pos (0U)
6590#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
6591#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
6592#define DMA2D_FGCOLR_GREEN_Pos (8U)
6593#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
6594#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
6595#define DMA2D_FGCOLR_RED_Pos (16U)
6596#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
6597#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
6598
6599/******************** Bit definition for DMA2D_BGPFCCR register *************/
6600
6601#define DMA2D_BGPFCCR_CM_Pos (0U)
6602#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
6603#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
6604#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
6605#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
6606#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
6607#define DMA2D_BGPFCCR_CM_3 0x00000008U
6608#define DMA2D_BGPFCCR_CCM_Pos (4U)
6609#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
6610#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
6611#define DMA2D_BGPFCCR_START_Pos (5U)
6612#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
6613#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
6614#define DMA2D_BGPFCCR_CS_Pos (8U)
6615#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
6616#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
6617#define DMA2D_BGPFCCR_AM_Pos (16U)
6618#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
6619#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
6620#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
6621#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
6622#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6623#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
6624#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
6625
6626/******************** Bit definition for DMA2D_BGCOLR register **************/
6627
6628#define DMA2D_BGCOLR_BLUE_Pos (0U)
6629#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
6630#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
6631#define DMA2D_BGCOLR_GREEN_Pos (8U)
6632#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
6633#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
6634#define DMA2D_BGCOLR_RED_Pos (16U)
6635#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
6636#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
6637
6638/******************** Bit definition for DMA2D_FGCMAR register **************/
6639
6640#define DMA2D_FGCMAR_MA_Pos (0U)
6641#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
6642#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
6643
6644/******************** Bit definition for DMA2D_BGCMAR register **************/
6645
6646#define DMA2D_BGCMAR_MA_Pos (0U)
6647#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
6648#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
6649
6650/******************** Bit definition for DMA2D_OPFCCR register **************/
6651
6652#define DMA2D_OPFCCR_CM_Pos (0U)
6653#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
6654#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
6655#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
6656#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
6657#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
6658
6659/******************** Bit definition for DMA2D_OCOLR register ***************/
6660
6662
6663#define DMA2D_OCOLR_BLUE_1 0x000000FFU
6664#define DMA2D_OCOLR_GREEN_1 0x0000FF00U
6665#define DMA2D_OCOLR_RED_1 0x00FF0000U
6666#define DMA2D_OCOLR_ALPHA_1 0xFF000000U
6667
6669#define DMA2D_OCOLR_BLUE_2 0x0000001FU
6670#define DMA2D_OCOLR_GREEN_2 0x000007E0U
6671#define DMA2D_OCOLR_RED_2 0x0000F800U
6672
6674#define DMA2D_OCOLR_BLUE_3 0x0000001FU
6675#define DMA2D_OCOLR_GREEN_3 0x000003E0U
6676#define DMA2D_OCOLR_RED_3 0x00007C00U
6677#define DMA2D_OCOLR_ALPHA_3 0x00008000U
6678
6680#define DMA2D_OCOLR_BLUE_4 0x0000000FU
6681#define DMA2D_OCOLR_GREEN_4 0x000000F0U
6682#define DMA2D_OCOLR_RED_4 0x00000F00U
6683#define DMA2D_OCOLR_ALPHA_4 0x0000F000U
6684
6685/******************** Bit definition for DMA2D_OMAR register ****************/
6686
6687#define DMA2D_OMAR_MA_Pos (0U)
6688#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
6689#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
6690
6691/******************** Bit definition for DMA2D_OOR register *****************/
6692
6693#define DMA2D_OOR_LO_Pos (0U)
6694#define DMA2D_OOR_LO_Msk (0x3FFFUL << DMA2D_OOR_LO_Pos)
6695#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
6696
6697/******************** Bit definition for DMA2D_NLR register *****************/
6698
6699#define DMA2D_NLR_NL_Pos (0U)
6700#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
6701#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
6702#define DMA2D_NLR_PL_Pos (16U)
6703#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
6704#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
6705
6706/******************** Bit definition for DMA2D_LWR register *****************/
6707
6708#define DMA2D_LWR_LW_Pos (0U)
6709#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
6710#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
6711
6712/******************** Bit definition for DMA2D_AMTCR register ***************/
6713
6714#define DMA2D_AMTCR_EN_Pos (0U)
6715#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
6716#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
6717#define DMA2D_AMTCR_DT_Pos (8U)
6718#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
6719#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
6720
6721/******************** Bit definition for DMA2D_FGCLUT register **************/
6722
6723/******************** Bit definition for DMA2D_BGCLUT register **************/
6724
6725
6726/******************************************************************************/
6727/* */
6728/* Display Serial Interface (DSI) */
6729/* */
6730/******************************************************************************/
6731/******************* Bit definition for DSI_VR register *****************/
6732#define DSI_VR_Pos (1U)
6733#define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos)
6734#define DSI_VR DSI_VR_Msk
6735
6736/******************* Bit definition for DSI_CR register *****************/
6737#define DSI_CR_EN_Pos (0U)
6738#define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos)
6739#define DSI_CR_EN DSI_CR_EN_Msk
6740
6741/******************* Bit definition for DSI_CCR register ****************/
6742#define DSI_CCR_TXECKDIV_Pos (0U)
6743#define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos)
6744#define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk
6745#define DSI_CCR_TXECKDIV0_Pos (0U)
6746#define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos)
6747#define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
6748#define DSI_CCR_TXECKDIV1_Pos (1U)
6749#define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos)
6750#define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
6751#define DSI_CCR_TXECKDIV2_Pos (2U)
6752#define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos)
6753#define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
6754#define DSI_CCR_TXECKDIV3_Pos (3U)
6755#define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos)
6756#define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
6757#define DSI_CCR_TXECKDIV4_Pos (4U)
6758#define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos)
6759#define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
6760#define DSI_CCR_TXECKDIV5_Pos (5U)
6761#define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos)
6762#define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
6763#define DSI_CCR_TXECKDIV6_Pos (6U)
6764#define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos)
6765#define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
6766#define DSI_CCR_TXECKDIV7_Pos (7U)
6767#define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos)
6768#define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
6769
6770#define DSI_CCR_TOCKDIV_Pos (8U)
6771#define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos)
6772#define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk
6773#define DSI_CCR_TOCKDIV0_Pos (8U)
6774#define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos)
6775#define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
6776#define DSI_CCR_TOCKDIV1_Pos (9U)
6777#define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos)
6778#define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
6779#define DSI_CCR_TOCKDIV2_Pos (10U)
6780#define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos)
6781#define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
6782#define DSI_CCR_TOCKDIV3_Pos (11U)
6783#define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos)
6784#define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
6785#define DSI_CCR_TOCKDIV4_Pos (12U)
6786#define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos)
6787#define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
6788#define DSI_CCR_TOCKDIV5_Pos (13U)
6789#define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos)
6790#define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
6791#define DSI_CCR_TOCKDIV6_Pos (14U)
6792#define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos)
6793#define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
6794#define DSI_CCR_TOCKDIV7_Pos (15U)
6795#define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos)
6796#define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
6797
6798/******************* Bit definition for DSI_LVCIDR register *************/
6799#define DSI_LVCIDR_VCID_Pos (0U)
6800#define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos)
6801#define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk
6802#define DSI_LVCIDR_VCID0_Pos (0U)
6803#define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos)
6804#define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
6805#define DSI_LVCIDR_VCID1_Pos (1U)
6806#define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos)
6807#define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
6808
6809/******************* Bit definition for DSI_LCOLCR register *************/
6810#define DSI_LCOLCR_COLC_Pos (0U)
6811#define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos)
6812#define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk
6813#define DSI_LCOLCR_COLC0_Pos (0U)
6814#define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos)
6815#define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
6816#define DSI_LCOLCR_COLC1_Pos (5U)
6817#define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos)
6818#define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
6819#define DSI_LCOLCR_COLC2_Pos (6U)
6820#define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos)
6821#define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
6822#define DSI_LCOLCR_COLC3_Pos (7U)
6823#define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos)
6824#define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
6825
6826#define DSI_LCOLCR_LPE_Pos (8U)
6827#define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos)
6828#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk
6829
6830/******************* Bit definition for DSI_LPCR register ***************/
6831#define DSI_LPCR_DEP_Pos (0U)
6832#define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos)
6833#define DSI_LPCR_DEP DSI_LPCR_DEP_Msk
6834#define DSI_LPCR_VSP_Pos (1U)
6835#define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos)
6836#define DSI_LPCR_VSP DSI_LPCR_VSP_Msk
6837#define DSI_LPCR_HSP_Pos (2U)
6838#define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos)
6839#define DSI_LPCR_HSP DSI_LPCR_HSP_Msk
6840
6841/******************* Bit definition for DSI_LPMCR register **************/
6842#define DSI_LPMCR_VLPSIZE_Pos (0U)
6843#define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)
6844#define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk
6845#define DSI_LPMCR_VLPSIZE0_Pos (0U)
6846#define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)
6847#define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
6848#define DSI_LPMCR_VLPSIZE1_Pos (1U)
6849#define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)
6850#define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
6851#define DSI_LPMCR_VLPSIZE2_Pos (2U)
6852#define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)
6853#define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
6854#define DSI_LPMCR_VLPSIZE3_Pos (3U)
6855#define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)
6856#define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
6857#define DSI_LPMCR_VLPSIZE4_Pos (4U)
6858#define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)
6859#define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
6860#define DSI_LPMCR_VLPSIZE5_Pos (5U)
6861#define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)
6862#define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
6863#define DSI_LPMCR_VLPSIZE6_Pos (6U)
6864#define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)
6865#define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
6866#define DSI_LPMCR_VLPSIZE7_Pos (7U)
6867#define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)
6868#define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
6869
6870#define DSI_LPMCR_LPSIZE_Pos (16U)
6871#define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos)
6872#define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk
6873#define DSI_LPMCR_LPSIZE0_Pos (16U)
6874#define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos)
6875#define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
6876#define DSI_LPMCR_LPSIZE1_Pos (17U)
6877#define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos)
6878#define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
6879#define DSI_LPMCR_LPSIZE2_Pos (18U)
6880#define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos)
6881#define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
6882#define DSI_LPMCR_LPSIZE3_Pos (19U)
6883#define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos)
6884#define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
6885#define DSI_LPMCR_LPSIZE4_Pos (20U)
6886#define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos)
6887#define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
6888#define DSI_LPMCR_LPSIZE5_Pos (21U)
6889#define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos)
6890#define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
6891#define DSI_LPMCR_LPSIZE6_Pos (22U)
6892#define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos)
6893#define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
6894#define DSI_LPMCR_LPSIZE7_Pos (23U)
6895#define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos)
6896#define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
6897
6898/******************* Bit definition for DSI_PCR register ****************/
6899#define DSI_PCR_ETTXE_Pos (0U)
6900#define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos)
6901#define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk
6902#define DSI_PCR_ETRXE_Pos (1U)
6903#define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos)
6904#define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk
6905#define DSI_PCR_BTAE_Pos (2U)
6906#define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos)
6907#define DSI_PCR_BTAE DSI_PCR_BTAE_Msk
6908#define DSI_PCR_ECCRXE_Pos (3U)
6909#define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos)
6910#define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk
6911#define DSI_PCR_CRCRXE_Pos (4U)
6912#define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos)
6913#define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk
6914
6915/******************* Bit definition for DSI_GVCIDR register *************/
6916#define DSI_GVCIDR_VCID_Pos (0U)
6917#define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos)
6918#define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk
6919#define DSI_GVCIDR_VCID0_Pos (0U)
6920#define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos)
6921#define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
6922#define DSI_GVCIDR_VCID1_Pos (1U)
6923#define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos)
6924#define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
6925
6926/******************* Bit definition for DSI_MCR register ****************/
6927#define DSI_MCR_CMDM_Pos (0U)
6928#define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos)
6929#define DSI_MCR_CMDM DSI_MCR_CMDM_Msk
6930
6931/******************* Bit definition for DSI_VMCR register ***************/
6932#define DSI_VMCR_VMT_Pos (0U)
6933#define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos)
6934#define DSI_VMCR_VMT DSI_VMCR_VMT_Msk
6935#define DSI_VMCR_VMT0_Pos (0U)
6936#define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos)
6937#define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
6938#define DSI_VMCR_VMT1_Pos (1U)
6939#define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos)
6940#define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
6941
6942#define DSI_VMCR_LPVSAE_Pos (8U)
6943#define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos)
6944#define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk
6945#define DSI_VMCR_LPVBPE_Pos (9U)
6946#define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos)
6947#define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk
6948#define DSI_VMCR_LPVFPE_Pos (10U)
6949#define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos)
6950#define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk
6951#define DSI_VMCR_LPVAE_Pos (11U)
6952#define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos)
6953#define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk
6954#define DSI_VMCR_LPHBPE_Pos (12U)
6955#define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos)
6956#define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk
6957#define DSI_VMCR_LPHFPE_Pos (13U)
6958#define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos)
6959#define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk
6960#define DSI_VMCR_FBTAAE_Pos (14U)
6961#define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos)
6962#define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk
6963#define DSI_VMCR_LPCE_Pos (15U)
6964#define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos)
6965#define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk
6966#define DSI_VMCR_PGE_Pos (16U)
6967#define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos)
6968#define DSI_VMCR_PGE DSI_VMCR_PGE_Msk
6969#define DSI_VMCR_PGM_Pos (20U)
6970#define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos)
6971#define DSI_VMCR_PGM DSI_VMCR_PGM_Msk
6972#define DSI_VMCR_PGO_Pos (24U)
6973#define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos)
6974#define DSI_VMCR_PGO DSI_VMCR_PGO_Msk
6975
6976/******************* Bit definition for DSI_VPCR register ***************/
6977#define DSI_VPCR_VPSIZE_Pos (0U)
6978#define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)
6979#define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk
6980#define DSI_VPCR_VPSIZE0_Pos (0U)
6981#define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos)
6982#define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
6983#define DSI_VPCR_VPSIZE1_Pos (1U)
6984#define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos)
6985#define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
6986#define DSI_VPCR_VPSIZE2_Pos (2U)
6987#define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos)
6988#define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
6989#define DSI_VPCR_VPSIZE3_Pos (3U)
6990#define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos)
6991#define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
6992#define DSI_VPCR_VPSIZE4_Pos (4U)
6993#define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos)
6994#define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
6995#define DSI_VPCR_VPSIZE5_Pos (5U)
6996#define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos)
6997#define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
6998#define DSI_VPCR_VPSIZE6_Pos (6U)
6999#define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos)
7000#define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
7001#define DSI_VPCR_VPSIZE7_Pos (7U)
7002#define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos)
7003#define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
7004#define DSI_VPCR_VPSIZE8_Pos (8U)
7005#define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos)
7006#define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
7007#define DSI_VPCR_VPSIZE9_Pos (9U)
7008#define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos)
7009#define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
7010#define DSI_VPCR_VPSIZE10_Pos (10U)
7011#define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos)
7012#define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
7013#define DSI_VPCR_VPSIZE11_Pos (11U)
7014#define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos)
7015#define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
7016#define DSI_VPCR_VPSIZE12_Pos (12U)
7017#define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos)
7018#define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
7019#define DSI_VPCR_VPSIZE13_Pos (13U)
7020#define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos)
7021#define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
7022
7023/******************* Bit definition for DSI_VCCR register ***************/
7024#define DSI_VCCR_NUMC_Pos (0U)
7025#define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos)
7026#define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk
7027#define DSI_VCCR_NUMC0_Pos (0U)
7028#define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos)
7029#define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
7030#define DSI_VCCR_NUMC1_Pos (1U)
7031#define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos)
7032#define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
7033#define DSI_VCCR_NUMC2_Pos (2U)
7034#define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos)
7035#define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
7036#define DSI_VCCR_NUMC3_Pos (3U)
7037#define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos)
7038#define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
7039#define DSI_VCCR_NUMC4_Pos (4U)
7040#define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos)
7041#define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
7042#define DSI_VCCR_NUMC5_Pos (5U)
7043#define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos)
7044#define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
7045#define DSI_VCCR_NUMC6_Pos (6U)
7046#define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos)
7047#define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
7048#define DSI_VCCR_NUMC7_Pos (7U)
7049#define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos)
7050#define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
7051#define DSI_VCCR_NUMC8_Pos (8U)
7052#define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos)
7053#define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
7054#define DSI_VCCR_NUMC9_Pos (9U)
7055#define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos)
7056#define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
7057#define DSI_VCCR_NUMC10_Pos (10U)
7058#define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos)
7059#define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
7060#define DSI_VCCR_NUMC11_Pos (11U)
7061#define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos)
7062#define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
7063#define DSI_VCCR_NUMC12_Pos (12U)
7064#define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos)
7065#define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
7066
7067/******************* Bit definition for DSI_VNPCR register **************/
7068#define DSI_VNPCR_NPSIZE_Pos (0U)
7069#define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)
7070#define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk
7071#define DSI_VNPCR_NPSIZE0_Pos (0U)
7072#define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos)
7073#define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
7074#define DSI_VNPCR_NPSIZE1_Pos (1U)
7075#define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos)
7076#define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
7077#define DSI_VNPCR_NPSIZE2_Pos (2U)
7078#define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos)
7079#define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
7080#define DSI_VNPCR_NPSIZE3_Pos (3U)
7081#define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos)
7082#define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
7083#define DSI_VNPCR_NPSIZE4_Pos (4U)
7084#define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos)
7085#define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
7086#define DSI_VNPCR_NPSIZE5_Pos (5U)
7087#define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos)
7088#define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
7089#define DSI_VNPCR_NPSIZE6_Pos (6U)
7090#define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos)
7091#define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
7092#define DSI_VNPCR_NPSIZE7_Pos (7U)
7093#define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos)
7094#define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
7095#define DSI_VNPCR_NPSIZE8_Pos (8U)
7096#define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos)
7097#define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
7098#define DSI_VNPCR_NPSIZE9_Pos (9U)
7099#define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos)
7100#define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
7101#define DSI_VNPCR_NPSIZE10_Pos (10U)
7102#define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos)
7103#define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
7104#define DSI_VNPCR_NPSIZE11_Pos (11U)
7105#define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos)
7106#define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
7107#define DSI_VNPCR_NPSIZE12_Pos (12U)
7108#define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos)
7109#define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
7110
7111/******************* Bit definition for DSI_VHSACR register *************/
7112#define DSI_VHSACR_HSA_Pos (0U)
7113#define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos)
7114#define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk
7115#define DSI_VHSACR_HSA0_Pos (0U)
7116#define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos)
7117#define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
7118#define DSI_VHSACR_HSA1_Pos (1U)
7119#define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos)
7120#define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
7121#define DSI_VHSACR_HSA2_Pos (2U)
7122#define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos)
7123#define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
7124#define DSI_VHSACR_HSA3_Pos (3U)
7125#define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos)
7126#define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
7127#define DSI_VHSACR_HSA4_Pos (4U)
7128#define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos)
7129#define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
7130#define DSI_VHSACR_HSA5_Pos (5U)
7131#define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos)
7132#define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
7133#define DSI_VHSACR_HSA6_Pos (6U)
7134#define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos)
7135#define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
7136#define DSI_VHSACR_HSA7_Pos (7U)
7137#define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos)
7138#define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
7139#define DSI_VHSACR_HSA8_Pos (8U)
7140#define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos)
7141#define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
7142#define DSI_VHSACR_HSA9_Pos (9U)
7143#define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos)
7144#define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
7145#define DSI_VHSACR_HSA10_Pos (10U)
7146#define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos)
7147#define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
7148#define DSI_VHSACR_HSA11_Pos (11U)
7149#define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos)
7150#define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
7151
7152/******************* Bit definition for DSI_VHBPCR register *************/
7153#define DSI_VHBPCR_HBP_Pos (0U)
7154#define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos)
7155#define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk
7156#define DSI_VHBPCR_HBP0_Pos (0U)
7157#define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos)
7158#define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
7159#define DSI_VHBPCR_HBP1_Pos (1U)
7160#define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos)
7161#define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
7162#define DSI_VHBPCR_HBP2_Pos (2U)
7163#define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos)
7164#define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
7165#define DSI_VHBPCR_HBP3_Pos (3U)
7166#define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos)
7167#define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
7168#define DSI_VHBPCR_HBP4_Pos (4U)
7169#define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos)
7170#define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
7171#define DSI_VHBPCR_HBP5_Pos (5U)
7172#define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos)
7173#define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
7174#define DSI_VHBPCR_HBP6_Pos (6U)
7175#define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos)
7176#define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
7177#define DSI_VHBPCR_HBP7_Pos (7U)
7178#define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos)
7179#define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
7180#define DSI_VHBPCR_HBP8_Pos (8U)
7181#define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos)
7182#define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
7183#define DSI_VHBPCR_HBP9_Pos (9U)
7184#define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos)
7185#define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
7186#define DSI_VHBPCR_HBP10_Pos (10U)
7187#define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos)
7188#define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
7189#define DSI_VHBPCR_HBP11_Pos (11U)
7190#define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos)
7191#define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
7192
7193/******************* Bit definition for DSI_VLCR register ***************/
7194#define DSI_VLCR_HLINE_Pos (0U)
7195#define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos)
7196#define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk
7197#define DSI_VLCR_HLINE0_Pos (0U)
7198#define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos)
7199#define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
7200#define DSI_VLCR_HLINE1_Pos (1U)
7201#define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos)
7202#define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
7203#define DSI_VLCR_HLINE2_Pos (2U)
7204#define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos)
7205#define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
7206#define DSI_VLCR_HLINE3_Pos (3U)
7207#define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos)
7208#define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
7209#define DSI_VLCR_HLINE4_Pos (4U)
7210#define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos)
7211#define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
7212#define DSI_VLCR_HLINE5_Pos (5U)
7213#define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos)
7214#define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
7215#define DSI_VLCR_HLINE6_Pos (6U)
7216#define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos)
7217#define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
7218#define DSI_VLCR_HLINE7_Pos (7U)
7219#define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos)
7220#define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
7221#define DSI_VLCR_HLINE8_Pos (8U)
7222#define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos)
7223#define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
7224#define DSI_VLCR_HLINE9_Pos (9U)
7225#define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos)
7226#define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
7227#define DSI_VLCR_HLINE10_Pos (10U)
7228#define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos)
7229#define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
7230#define DSI_VLCR_HLINE11_Pos (11U)
7231#define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos)
7232#define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
7233#define DSI_VLCR_HLINE12_Pos (12U)
7234#define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos)
7235#define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
7236#define DSI_VLCR_HLINE13_Pos (13U)
7237#define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos)
7238#define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
7239#define DSI_VLCR_HLINE14_Pos (14U)
7240#define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos)
7241#define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
7242
7243/******************* Bit definition for DSI_VVSACR register *************/
7244#define DSI_VVSACR_VSA_Pos (0U)
7245#define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos)
7246#define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk
7247#define DSI_VVSACR_VSA0_Pos (0U)
7248#define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos)
7249#define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
7250#define DSI_VVSACR_VSA1_Pos (1U)
7251#define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos)
7252#define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
7253#define DSI_VVSACR_VSA2_Pos (2U)
7254#define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos)
7255#define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
7256#define DSI_VVSACR_VSA3_Pos (3U)
7257#define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos)
7258#define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
7259#define DSI_VVSACR_VSA4_Pos (4U)
7260#define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos)
7261#define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
7262#define DSI_VVSACR_VSA5_Pos (5U)
7263#define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos)
7264#define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
7265#define DSI_VVSACR_VSA6_Pos (6U)
7266#define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos)
7267#define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
7268#define DSI_VVSACR_VSA7_Pos (7U)
7269#define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos)
7270#define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
7271#define DSI_VVSACR_VSA8_Pos (8U)
7272#define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos)
7273#define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
7274#define DSI_VVSACR_VSA9_Pos (9U)
7275#define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos)
7276#define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
7277
7278/******************* Bit definition for DSI_VVBPCR register *************/
7279#define DSI_VVBPCR_VBP_Pos (0U)
7280#define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos)
7281#define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk
7282#define DSI_VVBPCR_VBP0_Pos (0U)
7283#define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos)
7284#define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
7285#define DSI_VVBPCR_VBP1_Pos (1U)
7286#define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos)
7287#define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
7288#define DSI_VVBPCR_VBP2_Pos (2U)
7289#define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos)
7290#define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
7291#define DSI_VVBPCR_VBP3_Pos (3U)
7292#define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos)
7293#define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
7294#define DSI_VVBPCR_VBP4_Pos (4U)
7295#define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos)
7296#define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
7297#define DSI_VVBPCR_VBP5_Pos (5U)
7298#define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos)
7299#define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
7300#define DSI_VVBPCR_VBP6_Pos (6U)
7301#define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos)
7302#define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
7303#define DSI_VVBPCR_VBP7_Pos (7U)
7304#define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos)
7305#define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
7306#define DSI_VVBPCR_VBP8_Pos (8U)
7307#define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos)
7308#define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
7309#define DSI_VVBPCR_VBP9_Pos (9U)
7310#define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos)
7311#define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
7312
7313/******************* Bit definition for DSI_VVFPCR register *************/
7314#define DSI_VVFPCR_VFP_Pos (0U)
7315#define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos)
7316#define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk
7317#define DSI_VVFPCR_VFP0_Pos (0U)
7318#define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos)
7319#define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
7320#define DSI_VVFPCR_VFP1_Pos (1U)
7321#define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos)
7322#define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
7323#define DSI_VVFPCR_VFP2_Pos (2U)
7324#define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos)
7325#define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
7326#define DSI_VVFPCR_VFP3_Pos (3U)
7327#define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos)
7328#define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
7329#define DSI_VVFPCR_VFP4_Pos (4U)
7330#define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos)
7331#define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
7332#define DSI_VVFPCR_VFP5_Pos (5U)
7333#define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos)
7334#define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
7335#define DSI_VVFPCR_VFP6_Pos (6U)
7336#define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos)
7337#define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
7338#define DSI_VVFPCR_VFP7_Pos (7U)
7339#define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos)
7340#define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
7341#define DSI_VVFPCR_VFP8_Pos (8U)
7342#define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos)
7343#define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
7344#define DSI_VVFPCR_VFP9_Pos (9U)
7345#define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos)
7346#define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
7347
7348/******************* Bit definition for DSI_VVACR register **************/
7349#define DSI_VVACR_VA_Pos (0U)
7350#define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos)
7351#define DSI_VVACR_VA DSI_VVACR_VA_Msk
7352#define DSI_VVACR_VA0_Pos (0U)
7353#define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos)
7354#define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
7355#define DSI_VVACR_VA1_Pos (1U)
7356#define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos)
7357#define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
7358#define DSI_VVACR_VA2_Pos (2U)
7359#define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos)
7360#define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
7361#define DSI_VVACR_VA3_Pos (3U)
7362#define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos)
7363#define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
7364#define DSI_VVACR_VA4_Pos (4U)
7365#define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos)
7366#define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
7367#define DSI_VVACR_VA5_Pos (5U)
7368#define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos)
7369#define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
7370#define DSI_VVACR_VA6_Pos (6U)
7371#define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos)
7372#define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
7373#define DSI_VVACR_VA7_Pos (7U)
7374#define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos)
7375#define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
7376#define DSI_VVACR_VA8_Pos (8U)
7377#define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos)
7378#define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
7379#define DSI_VVACR_VA9_Pos (9U)
7380#define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos)
7381#define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
7382#define DSI_VVACR_VA10_Pos (10U)
7383#define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos)
7384#define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
7385#define DSI_VVACR_VA11_Pos (11U)
7386#define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos)
7387#define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
7388#define DSI_VVACR_VA12_Pos (12U)
7389#define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos)
7390#define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
7391#define DSI_VVACR_VA13_Pos (13U)
7392#define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos)
7393#define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
7394
7395/******************* Bit definition for DSI_LCCR register ***************/
7396#define DSI_LCCR_CMDSIZE_Pos (0U)
7397#define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)
7398#define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk
7399#define DSI_LCCR_CMDSIZE0_Pos (0U)
7400#define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos)
7401#define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
7402#define DSI_LCCR_CMDSIZE1_Pos (1U)
7403#define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos)
7404#define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
7405#define DSI_LCCR_CMDSIZE2_Pos (2U)
7406#define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos)
7407#define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
7408#define DSI_LCCR_CMDSIZE3_Pos (3U)
7409#define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos)
7410#define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
7411#define DSI_LCCR_CMDSIZE4_Pos (4U)
7412#define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos)
7413#define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
7414#define DSI_LCCR_CMDSIZE5_Pos (5U)
7415#define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos)
7416#define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
7417#define DSI_LCCR_CMDSIZE6_Pos (6U)
7418#define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos)
7419#define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
7420#define DSI_LCCR_CMDSIZE7_Pos (7U)
7421#define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos)
7422#define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
7423#define DSI_LCCR_CMDSIZE8_Pos (8U)
7424#define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos)
7425#define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
7426#define DSI_LCCR_CMDSIZE9_Pos (9U)
7427#define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos)
7428#define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
7429#define DSI_LCCR_CMDSIZE10_Pos (10U)
7430#define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos)
7431#define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
7432#define DSI_LCCR_CMDSIZE11_Pos (11U)
7433#define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos)
7434#define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
7435#define DSI_LCCR_CMDSIZE12_Pos (12U)
7436#define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos)
7437#define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
7438#define DSI_LCCR_CMDSIZE13_Pos (13U)
7439#define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos)
7440#define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
7441#define DSI_LCCR_CMDSIZE14_Pos (14U)
7442#define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos)
7443#define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
7444#define DSI_LCCR_CMDSIZE15_Pos (15U)
7445#define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos)
7446#define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
7447
7448/******************* Bit definition for DSI_CMCR register ***************/
7449#define DSI_CMCR_TEARE_Pos (0U)
7450#define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos)
7451#define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk
7452#define DSI_CMCR_ARE_Pos (1U)
7453#define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos)
7454#define DSI_CMCR_ARE DSI_CMCR_ARE_Msk
7455#define DSI_CMCR_GSW0TX_Pos (8U)
7456#define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos)
7457#define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk
7458#define DSI_CMCR_GSW1TX_Pos (9U)
7459#define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos)
7460#define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk
7461#define DSI_CMCR_GSW2TX_Pos (10U)
7462#define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos)
7463#define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk
7464#define DSI_CMCR_GSR0TX_Pos (11U)
7465#define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos)
7466#define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk
7467#define DSI_CMCR_GSR1TX_Pos (12U)
7468#define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos)
7469#define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk
7470#define DSI_CMCR_GSR2TX_Pos (13U)
7471#define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos)
7472#define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk
7473#define DSI_CMCR_GLWTX_Pos (14U)
7474#define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos)
7475#define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk
7476#define DSI_CMCR_DSW0TX_Pos (16U)
7477#define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos)
7478#define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk
7479#define DSI_CMCR_DSW1TX_Pos (17U)
7480#define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos)
7481#define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk
7482#define DSI_CMCR_DSR0TX_Pos (18U)
7483#define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos)
7484#define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk
7485#define DSI_CMCR_DLWTX_Pos (19U)
7486#define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos)
7487#define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk
7488#define DSI_CMCR_MRDPS_Pos (24U)
7489#define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos)
7490#define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk
7491
7492/******************* Bit definition for DSI_GHCR register ***************/
7493#define DSI_GHCR_DT_Pos (0U)
7494#define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos)
7495#define DSI_GHCR_DT DSI_GHCR_DT_Msk
7496#define DSI_GHCR_DT0_Pos (0U)
7497#define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos)
7498#define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
7499#define DSI_GHCR_DT1_Pos (1U)
7500#define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos)
7501#define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
7502#define DSI_GHCR_DT2_Pos (2U)
7503#define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos)
7504#define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
7505#define DSI_GHCR_DT3_Pos (3U)
7506#define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos)
7507#define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
7508#define DSI_GHCR_DT4_Pos (4U)
7509#define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos)
7510#define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
7511#define DSI_GHCR_DT5_Pos (5U)
7512#define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos)
7513#define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
7514
7515#define DSI_GHCR_VCID_Pos (6U)
7516#define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos)
7517#define DSI_GHCR_VCID DSI_GHCR_VCID_Msk
7518#define DSI_GHCR_VCID0_Pos (6U)
7519#define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos)
7520#define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
7521#define DSI_GHCR_VCID1_Pos (7U)
7522#define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos)
7523#define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
7524
7525#define DSI_GHCR_WCLSB_Pos (8U)
7526#define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos)
7527#define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk
7528#define DSI_GHCR_WCLSB0_Pos (8U)
7529#define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos)
7530#define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
7531#define DSI_GHCR_WCLSB1_Pos (9U)
7532#define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos)
7533#define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
7534#define DSI_GHCR_WCLSB2_Pos (10U)
7535#define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos)
7536#define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
7537#define DSI_GHCR_WCLSB3_Pos (11U)
7538#define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos)
7539#define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
7540#define DSI_GHCR_WCLSB4_Pos (12U)
7541#define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos)
7542#define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
7543#define DSI_GHCR_WCLSB5_Pos (13U)
7544#define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos)
7545#define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
7546#define DSI_GHCR_WCLSB6_Pos (14U)
7547#define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos)
7548#define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
7549#define DSI_GHCR_WCLSB7_Pos (15U)
7550#define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos)
7551#define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
7552
7553#define DSI_GHCR_WCMSB_Pos (16U)
7554#define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos)
7555#define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk
7556#define DSI_GHCR_WCMSB0_Pos (16U)
7557#define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos)
7558#define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
7559#define DSI_GHCR_WCMSB1_Pos (17U)
7560#define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos)
7561#define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
7562#define DSI_GHCR_WCMSB2_Pos (18U)
7563#define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos)
7564#define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
7565#define DSI_GHCR_WCMSB3_Pos (19U)
7566#define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos)
7567#define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
7568#define DSI_GHCR_WCMSB4_Pos (20U)
7569#define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos)
7570#define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
7571#define DSI_GHCR_WCMSB5_Pos (21U)
7572#define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos)
7573#define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
7574#define DSI_GHCR_WCMSB6_Pos (22U)
7575#define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos)
7576#define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
7577#define DSI_GHCR_WCMSB7_Pos (23U)
7578#define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos)
7579#define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
7580
7581/******************* Bit definition for DSI_GPDR register ***************/
7582#define DSI_GPDR_DATA1_Pos (0U)
7583#define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos)
7584#define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk
7585#define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos)
7586#define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos)
7587#define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos)
7588#define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos)
7589#define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos)
7590#define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos)
7591#define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos)
7592#define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos)
7593
7594#define DSI_GPDR_DATA2_Pos (8U)
7595#define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos)
7596#define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk
7597#define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos)
7598#define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos)
7599#define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos)
7600#define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos)
7601#define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos)
7602#define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos)
7603#define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos)
7604#define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos)
7605
7606#define DSI_GPDR_DATA3_Pos (16U)
7607#define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos)
7608#define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk
7609#define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos)
7610#define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos)
7611#define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos)
7612#define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos)
7613#define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos)
7614#define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos)
7615#define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos)
7616#define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos)
7617
7618#define DSI_GPDR_DATA4_Pos (24U)
7619#define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos)
7620#define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk
7621#define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos)
7622#define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos)
7623#define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos)
7624#define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos)
7625#define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos)
7626#define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos)
7627#define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos)
7628#define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos)
7629
7630/******************* Bit definition for DSI_GPSR register ***************/
7631#define DSI_GPSR_CMDFE_Pos (0U)
7632#define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos)
7633#define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk
7634#define DSI_GPSR_CMDFF_Pos (1U)
7635#define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos)
7636#define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk
7637#define DSI_GPSR_PWRFE_Pos (2U)
7638#define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos)
7639#define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk
7640#define DSI_GPSR_PWRFF_Pos (3U)
7641#define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos)
7642#define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk
7643#define DSI_GPSR_PRDFE_Pos (4U)
7644#define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos)
7645#define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk
7646#define DSI_GPSR_PRDFF_Pos (5U)
7647#define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos)
7648#define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk
7649#define DSI_GPSR_RCB_Pos (6U)
7650#define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos)
7651#define DSI_GPSR_RCB DSI_GPSR_RCB_Msk
7652
7653/******************* Bit definition for DSI_TCCR0 register **************/
7654#define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
7655#define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)
7656#define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk
7657#define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
7658#define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)
7659#define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
7660#define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
7661#define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)
7662#define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
7663#define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
7664#define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)
7665#define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
7666#define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
7667#define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)
7668#define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
7669#define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
7670#define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)
7671#define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
7672#define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
7673#define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)
7674#define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
7675#define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
7676#define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)
7677#define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
7678#define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
7679#define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)
7680#define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
7681#define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
7682#define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)
7683#define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
7684#define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
7685#define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)
7686#define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
7687#define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
7688#define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)
7689#define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
7690#define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
7691#define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)
7692#define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
7693#define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
7694#define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)
7695#define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
7696#define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
7697#define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)
7698#define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
7699#define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
7700#define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)
7701#define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
7702#define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
7703#define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)
7704#define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
7705
7706#define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
7707#define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)
7708#define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk
7709#define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
7710#define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)
7711#define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
7712#define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
7713#define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)
7714#define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
7715#define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
7716#define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)
7717#define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
7718#define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
7719#define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)
7720#define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
7721#define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
7722#define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)
7723#define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
7724#define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
7725#define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)
7726#define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
7727#define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
7728#define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)
7729#define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
7730#define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
7731#define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)
7732#define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
7733#define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
7734#define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)
7735#define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
7736#define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
7737#define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)
7738#define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
7739#define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
7740#define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)
7741#define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
7742#define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
7743#define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)
7744#define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
7745#define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
7746#define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)
7747#define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
7748#define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
7749#define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)
7750#define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
7751#define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
7752#define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)
7753#define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
7754#define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
7755#define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)
7756#define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
7757
7758/******************* Bit definition for DSI_TCCR1 register **************/
7759#define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
7760#define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)
7761#define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk
7762#define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
7763#define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)
7764#define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
7765#define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
7766#define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)
7767#define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
7768#define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
7769#define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)
7770#define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
7771#define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
7772#define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)
7773#define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
7774#define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
7775#define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)
7776#define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
7777#define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
7778#define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)
7779#define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
7780#define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
7781#define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)
7782#define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
7783#define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
7784#define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)
7785#define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
7786#define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
7787#define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)
7788#define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
7789#define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
7790#define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)
7791#define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
7792#define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
7793#define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)
7794#define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
7795#define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
7796#define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)
7797#define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
7798#define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
7799#define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)
7800#define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
7801#define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
7802#define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)
7803#define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
7804#define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
7805#define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)
7806#define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
7807#define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
7808#define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)
7809#define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
7810
7811/******************* Bit definition for DSI_TCCR2 register **************/
7812#define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
7813#define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)
7814#define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk
7815#define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
7816#define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)
7817#define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
7818#define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
7819#define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)
7820#define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
7821#define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
7822#define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)
7823#define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
7824#define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
7825#define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)
7826#define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
7827#define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
7828#define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)
7829#define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
7830#define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
7831#define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)
7832#define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
7833#define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
7834#define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)
7835#define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
7836#define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
7837#define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)
7838#define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
7839#define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
7840#define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)
7841#define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
7842#define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
7843#define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)
7844#define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
7845#define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
7846#define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)
7847#define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
7848#define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
7849#define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)
7850#define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
7851#define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
7852#define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)
7853#define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
7854#define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
7855#define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)
7856#define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
7857#define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
7858#define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)
7859#define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
7860#define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
7861#define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)
7862#define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
7863
7864/******************* Bit definition for DSI_TCCR3 register **************/
7865#define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
7866#define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)
7867#define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk
7868#define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
7869#define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)
7870#define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
7871#define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
7872#define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)
7873#define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
7874#define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
7875#define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)
7876#define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
7877#define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
7878#define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)
7879#define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
7880#define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
7881#define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)
7882#define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
7883#define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
7884#define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)
7885#define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
7886#define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
7887#define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)
7888#define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
7889#define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
7890#define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)
7891#define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
7892#define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
7893#define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)
7894#define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
7895#define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
7896#define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)
7897#define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
7898#define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
7899#define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)
7900#define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
7901#define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
7902#define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)
7903#define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
7904#define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
7905#define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)
7906#define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
7907#define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
7908#define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)
7909#define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
7910#define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
7911#define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)
7912#define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
7913#define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
7914#define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)
7915#define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
7916
7917#define DSI_TCCR3_PM_Pos (24U)
7918#define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos)
7919#define DSI_TCCR3_PM DSI_TCCR3_PM_Msk
7920
7921/******************* Bit definition for DSI_TCCR4 register **************/
7922#define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
7923#define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)
7924#define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk
7925#define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
7926#define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)
7927#define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
7928#define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
7929#define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)
7930#define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
7931#define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
7932#define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)
7933#define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
7934#define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
7935#define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)
7936#define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
7937#define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
7938#define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)
7939#define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
7940#define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
7941#define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)
7942#define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
7943#define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
7944#define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)
7945#define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
7946#define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
7947#define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)
7948#define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
7949#define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
7950#define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)
7951#define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
7952#define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
7953#define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)
7954#define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
7955#define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
7956#define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)
7957#define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
7958#define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
7959#define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)
7960#define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
7961#define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
7962#define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)
7963#define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
7964#define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
7965#define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)
7966#define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
7967#define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
7968#define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)
7969#define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
7970#define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
7971#define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)
7972#define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
7973
7974/******************* Bit definition for DSI_TCCR5 register **************/
7975#define DSI_TCCR5_BTA_TOCNT_Pos (0U)
7976#define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)
7977#define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk
7978#define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
7979#define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)
7980#define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
7981#define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
7982#define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)
7983#define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
7984#define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
7985#define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)
7986#define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
7987#define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
7988#define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)
7989#define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
7990#define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
7991#define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)
7992#define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
7993#define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
7994#define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)
7995#define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
7996#define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
7997#define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)
7998#define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
7999#define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
8000#define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)
8001#define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
8002#define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
8003#define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)
8004#define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
8005#define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
8006#define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)
8007#define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
8008#define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
8009#define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)
8010#define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
8011#define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
8012#define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)
8013#define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
8014#define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
8015#define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)
8016#define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
8017#define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
8018#define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)
8019#define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
8020#define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
8021#define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)
8022#define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
8023#define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
8024#define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)
8025#define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
8026
8027/******************* Bit definition for DSI_TDCR register ***************/
8028#define DSI_TDCR_3DM 0x00000003U
8029#define DSI_TDCR_3DM0 0x00000001U
8030#define DSI_TDCR_3DM1 0x00000002U
8031
8032#define DSI_TDCR_3DF 0x0000000CU
8033#define DSI_TDCR_3DF0 0x00000004U
8034#define DSI_TDCR_3DF1 0x00000008U
8035
8036#define DSI_TDCR_SVS_Pos (4U)
8037#define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos)
8038#define DSI_TDCR_SVS DSI_TDCR_SVS_Msk
8039#define DSI_TDCR_RF_Pos (5U)
8040#define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos)
8041#define DSI_TDCR_RF DSI_TDCR_RF_Msk
8042#define DSI_TDCR_S3DC_Pos (16U)
8043#define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos)
8044#define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk
8045
8046/******************* Bit definition for DSI_CLCR register ***************/
8047#define DSI_CLCR_DPCC_Pos (0U)
8048#define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos)
8049#define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk
8050#define DSI_CLCR_ACR_Pos (1U)
8051#define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos)
8052#define DSI_CLCR_ACR DSI_CLCR_ACR_Msk
8053
8054/******************* Bit definition for DSI_CLTCR register **************/
8055#define DSI_CLTCR_LP2HS_TIME_Pos (0U)
8056#define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)
8057#define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk
8058#define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
8059#define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)
8060#define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
8061#define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
8062#define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)
8063#define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
8064#define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
8065#define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)
8066#define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
8067#define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
8068#define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)
8069#define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
8070#define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
8071#define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)
8072#define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
8073#define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
8074#define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)
8075#define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
8076#define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
8077#define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)
8078#define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
8079#define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
8080#define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)
8081#define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
8082#define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
8083#define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)
8084#define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
8085#define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
8086#define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)
8087#define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
8088
8089#define DSI_CLTCR_HS2LP_TIME_Pos (16U)
8090#define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)
8091#define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk
8092#define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
8093#define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)
8094#define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
8095#define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
8096#define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)
8097#define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
8098#define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
8099#define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)
8100#define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
8101#define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
8102#define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)
8103#define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
8104#define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
8105#define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)
8106#define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
8107#define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
8108#define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)
8109#define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
8110#define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
8111#define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)
8112#define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
8113#define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
8114#define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)
8115#define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
8116#define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
8117#define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)
8118#define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
8119#define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
8120#define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)
8121#define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
8122
8123/******************* Bit definition for DSI_DLTCR register **************/
8124#define DSI_DLTCR_MRD_TIME_Pos (0U)
8125#define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)
8126#define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk
8127#define DSI_DLTCR_MRD_TIME0_Pos (0U)
8128#define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)
8129#define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
8130#define DSI_DLTCR_MRD_TIME1_Pos (1U)
8131#define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)
8132#define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
8133#define DSI_DLTCR_MRD_TIME2_Pos (2U)
8134#define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)
8135#define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
8136#define DSI_DLTCR_MRD_TIME3_Pos (3U)
8137#define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)
8138#define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
8139#define DSI_DLTCR_MRD_TIME4_Pos (4U)
8140#define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)
8141#define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
8142#define DSI_DLTCR_MRD_TIME5_Pos (5U)
8143#define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)
8144#define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
8145#define DSI_DLTCR_MRD_TIME6_Pos (6U)
8146#define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)
8147#define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
8148#define DSI_DLTCR_MRD_TIME7_Pos (7U)
8149#define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)
8150#define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
8151#define DSI_DLTCR_MRD_TIME8_Pos (8U)
8152#define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)
8153#define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
8154#define DSI_DLTCR_MRD_TIME9_Pos (9U)
8155#define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)
8156#define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
8157#define DSI_DLTCR_MRD_TIME10_Pos (10U)
8158#define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)
8159#define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
8160#define DSI_DLTCR_MRD_TIME11_Pos (11U)
8161#define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)
8162#define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
8163#define DSI_DLTCR_MRD_TIME12_Pos (12U)
8164#define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)
8165#define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
8166#define DSI_DLTCR_MRD_TIME13_Pos (13U)
8167#define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)
8168#define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
8169#define DSI_DLTCR_MRD_TIME14_Pos (14U)
8170#define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)
8171#define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
8172
8173#define DSI_DLTCR_LP2HS_TIME_Pos (16U)
8174#define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)
8175#define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk
8176#define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
8177#define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)
8178#define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
8179#define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
8180#define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)
8181#define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
8182#define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
8183#define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)
8184#define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
8185#define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
8186#define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)
8187#define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
8188#define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
8189#define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)
8190#define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
8191#define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
8192#define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)
8193#define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
8194#define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
8195#define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)
8196#define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
8197#define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
8198#define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)
8199#define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
8200
8201#define DSI_DLTCR_HS2LP_TIME_Pos (24U)
8202#define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)
8203#define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk
8204#define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
8205#define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)
8206#define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
8207#define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
8208#define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)
8209#define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
8210#define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
8211#define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)
8212#define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
8213#define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
8214#define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)
8215#define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
8216#define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
8217#define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)
8218#define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
8219#define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
8220#define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)
8221#define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
8222#define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
8223#define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)
8224#define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
8225#define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
8226#define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)
8227#define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
8228
8229/******************* Bit definition for DSI_PCTLR register **************/
8230#define DSI_PCTLR_DEN_Pos (1U)
8231#define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos)
8232#define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk
8233#define DSI_PCTLR_CKE_Pos (2U)
8234#define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos)
8235#define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk
8236
8237/******************* Bit definition for DSI_PCONFR register *************/
8238#define DSI_PCONFR_NL_Pos (0U)
8239#define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos)
8240#define DSI_PCONFR_NL DSI_PCONFR_NL_Msk
8241#define DSI_PCONFR_NL0_Pos (0U)
8242#define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos)
8243#define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
8244#define DSI_PCONFR_NL1_Pos (1U)
8245#define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos)
8246#define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
8247
8248#define DSI_PCONFR_SW_TIME_Pos (8U)
8249#define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos)
8250#define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk
8251#define DSI_PCONFR_SW_TIME0_Pos (8U)
8252#define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos)
8253#define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
8254#define DSI_PCONFR_SW_TIME1_Pos (9U)
8255#define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos)
8256#define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
8257#define DSI_PCONFR_SW_TIME2_Pos (10U)
8258#define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos)
8259#define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
8260#define DSI_PCONFR_SW_TIME3_Pos (11U)
8261#define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos)
8262#define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
8263#define DSI_PCONFR_SW_TIME4_Pos (12U)
8264#define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos)
8265#define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
8266#define DSI_PCONFR_SW_TIME5_Pos (13U)
8267#define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos)
8268#define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
8269#define DSI_PCONFR_SW_TIME6_Pos (14U)
8270#define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos)
8271#define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
8272#define DSI_PCONFR_SW_TIME7_Pos (15U)
8273#define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos)
8274#define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
8275
8276/******************* Bit definition for DSI_PUCR register ***************/
8277#define DSI_PUCR_URCL_Pos (0U)
8278#define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos)
8279#define DSI_PUCR_URCL DSI_PUCR_URCL_Msk
8280#define DSI_PUCR_UECL_Pos (1U)
8281#define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos)
8282#define DSI_PUCR_UECL DSI_PUCR_UECL_Msk
8283#define DSI_PUCR_URDL_Pos (2U)
8284#define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos)
8285#define DSI_PUCR_URDL DSI_PUCR_URDL_Msk
8286#define DSI_PUCR_UEDL_Pos (3U)
8287#define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos)
8288#define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk
8289
8290/******************* Bit definition for DSI_PTTCR register **************/
8291#define DSI_PTTCR_TX_TRIG_Pos (0U)
8292#define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos)
8293#define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk
8294#define DSI_PTTCR_TX_TRIG0_Pos (0U)
8295#define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)
8296#define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
8297#define DSI_PTTCR_TX_TRIG1_Pos (1U)
8298#define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)
8299#define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
8300#define DSI_PTTCR_TX_TRIG2_Pos (2U)
8301#define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)
8302#define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
8303#define DSI_PTTCR_TX_TRIG3_Pos (3U)
8304#define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)
8305#define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
8306
8307/******************* Bit definition for DSI_PSR register ****************/
8308#define DSI_PSR_PD_Pos (1U)
8309#define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos)
8310#define DSI_PSR_PD DSI_PSR_PD_Msk
8311#define DSI_PSR_PSSC_Pos (2U)
8312#define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos)
8313#define DSI_PSR_PSSC DSI_PSR_PSSC_Msk
8314#define DSI_PSR_UANC_Pos (3U)
8315#define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos)
8316#define DSI_PSR_UANC DSI_PSR_UANC_Msk
8317#define DSI_PSR_PSS0_Pos (4U)
8318#define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos)
8319#define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk
8320#define DSI_PSR_UAN0_Pos (5U)
8321#define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos)
8322#define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk
8323#define DSI_PSR_RUE0_Pos (6U)
8324#define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos)
8325#define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk
8326#define DSI_PSR_PSS1_Pos (7U)
8327#define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos)
8328#define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk
8329#define DSI_PSR_UAN1_Pos (8U)
8330#define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos)
8331#define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk
8332
8333/******************* Bit definition for DSI_ISR0 register ***************/
8334#define DSI_ISR0_AE0_Pos (0U)
8335#define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos)
8336#define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk
8337#define DSI_ISR0_AE1_Pos (1U)
8338#define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos)
8339#define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk
8340#define DSI_ISR0_AE2_Pos (2U)
8341#define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos)
8342#define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk
8343#define DSI_ISR0_AE3_Pos (3U)
8344#define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos)
8345#define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk
8346#define DSI_ISR0_AE4_Pos (4U)
8347#define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos)
8348#define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk
8349#define DSI_ISR0_AE5_Pos (5U)
8350#define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos)
8351#define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk
8352#define DSI_ISR0_AE6_Pos (6U)
8353#define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos)
8354#define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk
8355#define DSI_ISR0_AE7_Pos (7U)
8356#define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos)
8357#define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk
8358#define DSI_ISR0_AE8_Pos (8U)
8359#define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos)
8360#define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk
8361#define DSI_ISR0_AE9_Pos (9U)
8362#define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos)
8363#define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk
8364#define DSI_ISR0_AE10_Pos (10U)
8365#define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos)
8366#define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk
8367#define DSI_ISR0_AE11_Pos (11U)
8368#define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos)
8369#define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk
8370#define DSI_ISR0_AE12_Pos (12U)
8371#define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos)
8372#define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk
8373#define DSI_ISR0_AE13_Pos (13U)
8374#define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos)
8375#define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk
8376#define DSI_ISR0_AE14_Pos (14U)
8377#define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos)
8378#define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk
8379#define DSI_ISR0_AE15_Pos (15U)
8380#define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos)
8381#define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk
8382#define DSI_ISR0_PE0_Pos (16U)
8383#define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos)
8384#define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk
8385#define DSI_ISR0_PE1_Pos (17U)
8386#define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos)
8387#define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk
8388#define DSI_ISR0_PE2_Pos (18U)
8389#define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos)
8390#define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk
8391#define DSI_ISR0_PE3_Pos (19U)
8392#define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos)
8393#define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk
8394#define DSI_ISR0_PE4_Pos (20U)
8395#define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos)
8396#define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk
8397
8398/******************* Bit definition for DSI_ISR1 register ***************/
8399#define DSI_ISR1_TOHSTX_Pos (0U)
8400#define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos)
8401#define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk
8402#define DSI_ISR1_TOLPRX_Pos (1U)
8403#define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos)
8404#define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk
8405#define DSI_ISR1_ECCSE_Pos (2U)
8406#define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos)
8407#define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk
8408#define DSI_ISR1_ECCME_Pos (3U)
8409#define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos)
8410#define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk
8411#define DSI_ISR1_CRCE_Pos (4U)
8412#define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos)
8413#define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk
8414#define DSI_ISR1_PSE_Pos (5U)
8415#define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos)
8416#define DSI_ISR1_PSE DSI_ISR1_PSE_Msk
8417#define DSI_ISR1_EOTPE_Pos (6U)
8418#define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos)
8419#define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk
8420#define DSI_ISR1_LPWRE_Pos (7U)
8421#define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos)
8422#define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk
8423#define DSI_ISR1_GCWRE_Pos (8U)
8424#define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos)
8425#define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk
8426#define DSI_ISR1_GPWRE_Pos (9U)
8427#define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos)
8428#define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk
8429#define DSI_ISR1_GPTXE_Pos (10U)
8430#define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos)
8431#define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk
8432#define DSI_ISR1_GPRDE_Pos (11U)
8433#define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos)
8434#define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk
8435#define DSI_ISR1_GPRXE_Pos (12U)
8436#define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos)
8437#define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk
8438
8439/******************* Bit definition for DSI_IER0 register ***************/
8440#define DSI_IER0_AE0IE_Pos (0U)
8441#define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos)
8442#define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk
8443#define DSI_IER0_AE1IE_Pos (1U)
8444#define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos)
8445#define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk
8446#define DSI_IER0_AE2IE_Pos (2U)
8447#define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos)
8448#define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk
8449#define DSI_IER0_AE3IE_Pos (3U)
8450#define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos)
8451#define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk
8452#define DSI_IER0_AE4IE_Pos (4U)
8453#define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos)
8454#define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk
8455#define DSI_IER0_AE5IE_Pos (5U)
8456#define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos)
8457#define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk
8458#define DSI_IER0_AE6IE_Pos (6U)
8459#define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos)
8460#define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk
8461#define DSI_IER0_AE7IE_Pos (7U)
8462#define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos)
8463#define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk
8464#define DSI_IER0_AE8IE_Pos (8U)
8465#define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos)
8466#define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk
8467#define DSI_IER0_AE9IE_Pos (9U)
8468#define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos)
8469#define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk
8470#define DSI_IER0_AE10IE_Pos (10U)
8471#define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos)
8472#define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk
8473#define DSI_IER0_AE11IE_Pos (11U)
8474#define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos)
8475#define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk
8476#define DSI_IER0_AE12IE_Pos (12U)
8477#define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos)
8478#define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk
8479#define DSI_IER0_AE13IE_Pos (13U)
8480#define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos)
8481#define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk
8482#define DSI_IER0_AE14IE_Pos (14U)
8483#define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos)
8484#define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk
8485#define DSI_IER0_AE15IE_Pos (15U)
8486#define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos)
8487#define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk
8488#define DSI_IER0_PE0IE_Pos (16U)
8489#define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos)
8490#define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk
8491#define DSI_IER0_PE1IE_Pos (17U)
8492#define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos)
8493#define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk
8494#define DSI_IER0_PE2IE_Pos (18U)
8495#define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos)
8496#define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk
8497#define DSI_IER0_PE3IE_Pos (19U)
8498#define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos)
8499#define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk
8500#define DSI_IER0_PE4IE_Pos (20U)
8501#define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos)
8502#define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk
8503
8504/******************* Bit definition for DSI_IER1 register ***************/
8505#define DSI_IER1_TOHSTXIE_Pos (0U)
8506#define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos)
8507#define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk
8508#define DSI_IER1_TOLPRXIE_Pos (1U)
8509#define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos)
8510#define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk
8511#define DSI_IER1_ECCSEIE_Pos (2U)
8512#define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos)
8513#define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk
8514#define DSI_IER1_ECCMEIE_Pos (3U)
8515#define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos)
8516#define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk
8517#define DSI_IER1_CRCEIE_Pos (4U)
8518#define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos)
8519#define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk
8520#define DSI_IER1_PSEIE_Pos (5U)
8521#define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos)
8522#define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk
8523#define DSI_IER1_EOTPEIE_Pos (6U)
8524#define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos)
8525#define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk
8526#define DSI_IER1_LPWREIE_Pos (7U)
8527#define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos)
8528#define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk
8529#define DSI_IER1_GCWREIE_Pos (8U)
8530#define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos)
8531#define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk
8532#define DSI_IER1_GPWREIE_Pos (9U)
8533#define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos)
8534#define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk
8535#define DSI_IER1_GPTXEIE_Pos (10U)
8536#define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos)
8537#define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk
8538#define DSI_IER1_GPRDEIE_Pos (11U)
8539#define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos)
8540#define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk
8541#define DSI_IER1_GPRXEIE_Pos (12U)
8542#define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos)
8543#define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk
8544
8545/******************* Bit definition for DSI_FIR0 register ***************/
8546#define DSI_FIR0_FAE0_Pos (0U)
8547#define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos)
8548#define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk
8549#define DSI_FIR0_FAE1_Pos (1U)
8550#define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos)
8551#define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk
8552#define DSI_FIR0_FAE2_Pos (2U)
8553#define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos)
8554#define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk
8555#define DSI_FIR0_FAE3_Pos (3U)
8556#define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos)
8557#define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk
8558#define DSI_FIR0_FAE4_Pos (4U)
8559#define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos)
8560#define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk
8561#define DSI_FIR0_FAE5_Pos (5U)
8562#define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos)
8563#define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk
8564#define DSI_FIR0_FAE6_Pos (6U)
8565#define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos)
8566#define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk
8567#define DSI_FIR0_FAE7_Pos (7U)
8568#define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos)
8569#define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk
8570#define DSI_FIR0_FAE8_Pos (8U)
8571#define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos)
8572#define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk
8573#define DSI_FIR0_FAE9_Pos (9U)
8574#define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos)
8575#define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk
8576#define DSI_FIR0_FAE10_Pos (10U)
8577#define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos)
8578#define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk
8579#define DSI_FIR0_FAE11_Pos (11U)
8580#define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos)
8581#define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk
8582#define DSI_FIR0_FAE12_Pos (12U)
8583#define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos)
8584#define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk
8585#define DSI_FIR0_FAE13_Pos (13U)
8586#define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos)
8587#define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk
8588#define DSI_FIR0_FAE14_Pos (14U)
8589#define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos)
8590#define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk
8591#define DSI_FIR0_FAE15_Pos (15U)
8592#define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos)
8593#define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk
8594#define DSI_FIR0_FPE0_Pos (16U)
8595#define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos)
8596#define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk
8597#define DSI_FIR0_FPE1_Pos (17U)
8598#define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos)
8599#define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk
8600#define DSI_FIR0_FPE2_Pos (18U)
8601#define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos)
8602#define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk
8603#define DSI_FIR0_FPE3_Pos (19U)
8604#define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos)
8605#define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk
8606#define DSI_FIR0_FPE4_Pos (20U)
8607#define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos)
8608#define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk
8609
8610/******************* Bit definition for DSI_FIR1 register ***************/
8611#define DSI_FIR1_FTOHSTX_Pos (0U)
8612#define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos)
8613#define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk
8614#define DSI_FIR1_FTOLPRX_Pos (1U)
8615#define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos)
8616#define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk
8617#define DSI_FIR1_FECCSE_Pos (2U)
8618#define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos)
8619#define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk
8620#define DSI_FIR1_FECCME_Pos (3U)
8621#define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos)
8622#define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk
8623#define DSI_FIR1_FCRCE_Pos (4U)
8624#define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos)
8625#define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk
8626#define DSI_FIR1_FPSE_Pos (5U)
8627#define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos)
8628#define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk
8629#define DSI_FIR1_FEOTPE_Pos (6U)
8630#define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos)
8631#define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk
8632#define DSI_FIR1_FLPWRE_Pos (7U)
8633#define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos)
8634#define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk
8635#define DSI_FIR1_FGCWRE_Pos (8U)
8636#define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos)
8637#define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk
8638#define DSI_FIR1_FGPWRE_Pos (9U)
8639#define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos)
8640#define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk
8641#define DSI_FIR1_FGPTXE_Pos (10U)
8642#define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos)
8643#define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk
8644#define DSI_FIR1_FGPRDE_Pos (11U)
8645#define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos)
8646#define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk
8647#define DSI_FIR1_FGPRXE_Pos (12U)
8648#define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos)
8649#define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk
8650
8651/******************* Bit definition for DSI_VSCR register ***************/
8652#define DSI_VSCR_EN_Pos (0U)
8653#define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos)
8654#define DSI_VSCR_EN DSI_VSCR_EN_Msk
8655#define DSI_VSCR_UR_Pos (8U)
8656#define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos)
8657#define DSI_VSCR_UR DSI_VSCR_UR_Msk
8658
8659/******************* Bit definition for DSI_LCVCIDR register ************/
8660#define DSI_LCVCIDR_VCID_Pos (0U)
8661#define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos)
8662#define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk
8663#define DSI_LCVCIDR_VCID0_Pos (0U)
8664#define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos)
8665#define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
8666#define DSI_LCVCIDR_VCID1_Pos (1U)
8667#define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos)
8668#define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
8669
8670/******************* Bit definition for DSI_LCCCR register **************/
8671#define DSI_LCCCR_COLC_Pos (0U)
8672#define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos)
8673#define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk
8674#define DSI_LCCCR_COLC0_Pos (0U)
8675#define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos)
8676#define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
8677#define DSI_LCCCR_COLC1_Pos (1U)
8678#define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos)
8679#define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
8680#define DSI_LCCCR_COLC2_Pos (2U)
8681#define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos)
8682#define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
8683#define DSI_LCCCR_COLC3_Pos (3U)
8684#define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos)
8685#define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
8686
8687#define DSI_LCCCR_LPE_Pos (8U)
8688#define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos)
8689#define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk
8690
8691/******************* Bit definition for DSI_LPMCCR register *************/
8692#define DSI_LPMCCR_VLPSIZE_Pos (0U)
8693#define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)
8694#define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk
8695#define DSI_LPMCCR_VLPSIZE0_Pos (0U)
8696#define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)
8697#define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
8698#define DSI_LPMCCR_VLPSIZE1_Pos (1U)
8699#define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)
8700#define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
8701#define DSI_LPMCCR_VLPSIZE2_Pos (2U)
8702#define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)
8703#define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
8704#define DSI_LPMCCR_VLPSIZE3_Pos (3U)
8705#define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)
8706#define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
8707#define DSI_LPMCCR_VLPSIZE4_Pos (4U)
8708#define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)
8709#define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
8710#define DSI_LPMCCR_VLPSIZE5_Pos (5U)
8711#define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)
8712#define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
8713#define DSI_LPMCCR_VLPSIZE6_Pos (6U)
8714#define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)
8715#define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
8716#define DSI_LPMCCR_VLPSIZE7_Pos (7U)
8717#define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)
8718#define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
8719
8720#define DSI_LPMCCR_LPSIZE_Pos (16U)
8721#define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)
8722#define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk
8723#define DSI_LPMCCR_LPSIZE0_Pos (16U)
8724#define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)
8725#define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
8726#define DSI_LPMCCR_LPSIZE1_Pos (17U)
8727#define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)
8728#define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
8729#define DSI_LPMCCR_LPSIZE2_Pos (18U)
8730#define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)
8731#define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
8732#define DSI_LPMCCR_LPSIZE3_Pos (19U)
8733#define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)
8734#define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
8735#define DSI_LPMCCR_LPSIZE4_Pos (20U)
8736#define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)
8737#define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
8738#define DSI_LPMCCR_LPSIZE5_Pos (21U)
8739#define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)
8740#define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
8741#define DSI_LPMCCR_LPSIZE6_Pos (22U)
8742#define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)
8743#define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
8744#define DSI_LPMCCR_LPSIZE7_Pos (23U)
8745#define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)
8746#define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
8747
8748/******************* Bit definition for DSI_VMCCR register **************/
8749#define DSI_VMCCR_VMT_Pos (0U)
8750#define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos)
8751#define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk
8752#define DSI_VMCCR_VMT0_Pos (0U)
8753#define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos)
8754#define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
8755#define DSI_VMCCR_VMT1_Pos (1U)
8756#define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos)
8757#define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
8758
8759#define DSI_VMCCR_LPVSAE_Pos (8U)
8760#define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos)
8761#define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk
8762#define DSI_VMCCR_LPVBPE_Pos (9U)
8763#define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos)
8764#define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk
8765#define DSI_VMCCR_LPVFPE_Pos (10U)
8766#define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos)
8767#define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk
8768#define DSI_VMCCR_LPVAE_Pos (11U)
8769#define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos)
8770#define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk
8771#define DSI_VMCCR_LPHBPE_Pos (12U)
8772#define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos)
8773#define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk
8774#define DSI_VMCCR_LPHFE_Pos (13U)
8775#define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos)
8776#define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk
8777#define DSI_VMCCR_FBTAAE_Pos (14U)
8778#define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos)
8779#define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk
8780#define DSI_VMCCR_LPCE_Pos (15U)
8781#define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos)
8782#define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk
8783
8784/******************* Bit definition for DSI_VPCCR register **************/
8785#define DSI_VPCCR_VPSIZE_Pos (0U)
8786#define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)
8787#define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk
8788#define DSI_VPCCR_VPSIZE0_Pos (0U)
8789#define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos)
8790#define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
8791#define DSI_VPCCR_VPSIZE1_Pos (1U)
8792#define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos)
8793#define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
8794#define DSI_VPCCR_VPSIZE2_Pos (2U)
8795#define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos)
8796#define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
8797#define DSI_VPCCR_VPSIZE3_Pos (3U)
8798#define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos)
8799#define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
8800#define DSI_VPCCR_VPSIZE4_Pos (4U)
8801#define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos)
8802#define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
8803#define DSI_VPCCR_VPSIZE5_Pos (5U)
8804#define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos)
8805#define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
8806#define DSI_VPCCR_VPSIZE6_Pos (6U)
8807#define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos)
8808#define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
8809#define DSI_VPCCR_VPSIZE7_Pos (7U)
8810#define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos)
8811#define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
8812#define DSI_VPCCR_VPSIZE8_Pos (8U)
8813#define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos)
8814#define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
8815#define DSI_VPCCR_VPSIZE9_Pos (9U)
8816#define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos)
8817#define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
8818#define DSI_VPCCR_VPSIZE10_Pos (10U)
8819#define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos)
8820#define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
8821#define DSI_VPCCR_VPSIZE11_Pos (11U)
8822#define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos)
8823#define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
8824#define DSI_VPCCR_VPSIZE12_Pos (12U)
8825#define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos)
8826#define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
8827#define DSI_VPCCR_VPSIZE13_Pos (13U)
8828#define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos)
8829#define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
8830
8831/******************* Bit definition for DSI_VCCCR register **************/
8832#define DSI_VCCCR_NUMC_Pos (0U)
8833#define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos)
8834#define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk
8835#define DSI_VCCCR_NUMC0_Pos (0U)
8836#define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos)
8837#define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
8838#define DSI_VCCCR_NUMC1_Pos (1U)
8839#define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos)
8840#define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
8841#define DSI_VCCCR_NUMC2_Pos (2U)
8842#define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos)
8843#define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
8844#define DSI_VCCCR_NUMC3_Pos (3U)
8845#define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos)
8846#define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
8847#define DSI_VCCCR_NUMC4_Pos (4U)
8848#define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos)
8849#define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
8850#define DSI_VCCCR_NUMC5_Pos (5U)
8851#define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos)
8852#define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
8853#define DSI_VCCCR_NUMC6_Pos (6U)
8854#define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos)
8855#define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
8856#define DSI_VCCCR_NUMC7_Pos (7U)
8857#define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos)
8858#define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
8859#define DSI_VCCCR_NUMC8_Pos (8U)
8860#define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos)
8861#define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
8862#define DSI_VCCCR_NUMC9_Pos (9U)
8863#define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos)
8864#define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
8865#define DSI_VCCCR_NUMC10_Pos (10U)
8866#define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos)
8867#define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
8868#define DSI_VCCCR_NUMC11_Pos (11U)
8869#define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos)
8870#define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
8871#define DSI_VCCCR_NUMC12_Pos (12U)
8872#define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos)
8873#define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
8874
8875/******************* Bit definition for DSI_VNPCCR register *************/
8876#define DSI_VNPCCR_NPSIZE_Pos (0U)
8877#define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)
8878#define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk
8879#define DSI_VNPCCR_NPSIZE0_Pos (0U)
8880#define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)
8881#define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
8882#define DSI_VNPCCR_NPSIZE1_Pos (1U)
8883#define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)
8884#define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
8885#define DSI_VNPCCR_NPSIZE2_Pos (2U)
8886#define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)
8887#define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
8888#define DSI_VNPCCR_NPSIZE3_Pos (3U)
8889#define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)
8890#define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
8891#define DSI_VNPCCR_NPSIZE4_Pos (4U)
8892#define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)
8893#define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
8894#define DSI_VNPCCR_NPSIZE5_Pos (5U)
8895#define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)
8896#define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
8897#define DSI_VNPCCR_NPSIZE6_Pos (6U)
8898#define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)
8899#define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
8900#define DSI_VNPCCR_NPSIZE7_Pos (7U)
8901#define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)
8902#define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
8903#define DSI_VNPCCR_NPSIZE8_Pos (8U)
8904#define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)
8905#define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
8906#define DSI_VNPCCR_NPSIZE9_Pos (9U)
8907#define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)
8908#define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
8909#define DSI_VNPCCR_NPSIZE10_Pos (10U)
8910#define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)
8911#define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
8912#define DSI_VNPCCR_NPSIZE11_Pos (11U)
8913#define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)
8914#define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
8915#define DSI_VNPCCR_NPSIZE12_Pos (12U)
8916#define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)
8917#define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
8918
8919/******************* Bit definition for DSI_VHSACCR register ************/
8920#define DSI_VHSACCR_HSA_Pos (0U)
8921#define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos)
8922#define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk
8923#define DSI_VHSACCR_HSA0_Pos (0U)
8924#define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos)
8925#define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
8926#define DSI_VHSACCR_HSA1_Pos (1U)
8927#define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos)
8928#define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
8929#define DSI_VHSACCR_HSA2_Pos (2U)
8930#define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos)
8931#define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
8932#define DSI_VHSACCR_HSA3_Pos (3U)
8933#define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos)
8934#define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
8935#define DSI_VHSACCR_HSA4_Pos (4U)
8936#define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos)
8937#define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
8938#define DSI_VHSACCR_HSA5_Pos (5U)
8939#define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos)
8940#define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
8941#define DSI_VHSACCR_HSA6_Pos (6U)
8942#define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos)
8943#define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
8944#define DSI_VHSACCR_HSA7_Pos (7U)
8945#define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos)
8946#define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
8947#define DSI_VHSACCR_HSA8_Pos (8U)
8948#define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos)
8949#define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
8950#define DSI_VHSACCR_HSA9_Pos (9U)
8951#define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos)
8952#define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
8953#define DSI_VHSACCR_HSA10_Pos (10U)
8954#define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos)
8955#define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
8956#define DSI_VHSACCR_HSA11_Pos (11U)
8957#define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos)
8958#define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
8959
8960/******************* Bit definition for DSI_VHBPCCR register ************/
8961#define DSI_VHBPCCR_HBP_Pos (0U)
8962#define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos)
8963#define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk
8964#define DSI_VHBPCCR_HBP0_Pos (0U)
8965#define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos)
8966#define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
8967#define DSI_VHBPCCR_HBP1_Pos (1U)
8968#define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos)
8969#define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
8970#define DSI_VHBPCCR_HBP2_Pos (2U)
8971#define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos)
8972#define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
8973#define DSI_VHBPCCR_HBP3_Pos (3U)
8974#define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos)
8975#define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
8976#define DSI_VHBPCCR_HBP4_Pos (4U)
8977#define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos)
8978#define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
8979#define DSI_VHBPCCR_HBP5_Pos (5U)
8980#define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos)
8981#define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
8982#define DSI_VHBPCCR_HBP6_Pos (6U)
8983#define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos)
8984#define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
8985#define DSI_VHBPCCR_HBP7_Pos (7U)
8986#define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos)
8987#define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
8988#define DSI_VHBPCCR_HBP8_Pos (8U)
8989#define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos)
8990#define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
8991#define DSI_VHBPCCR_HBP9_Pos (9U)
8992#define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos)
8993#define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
8994#define DSI_VHBPCCR_HBP10_Pos (10U)
8995#define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos)
8996#define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
8997#define DSI_VHBPCCR_HBP11_Pos (11U)
8998#define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos)
8999#define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
9000
9001/******************* Bit definition for DSI_VLCCR register **************/
9002#define DSI_VLCCR_HLINE_Pos (0U)
9003#define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos)
9004#define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk
9005#define DSI_VLCCR_HLINE0_Pos (0U)
9006#define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos)
9007#define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
9008#define DSI_VLCCR_HLINE1_Pos (1U)
9009#define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos)
9010#define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
9011#define DSI_VLCCR_HLINE2_Pos (2U)
9012#define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos)
9013#define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
9014#define DSI_VLCCR_HLINE3_Pos (3U)
9015#define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos)
9016#define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
9017#define DSI_VLCCR_HLINE4_Pos (4U)
9018#define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos)
9019#define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
9020#define DSI_VLCCR_HLINE5_Pos (5U)
9021#define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos)
9022#define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
9023#define DSI_VLCCR_HLINE6_Pos (6U)
9024#define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos)
9025#define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
9026#define DSI_VLCCR_HLINE7_Pos (7U)
9027#define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos)
9028#define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
9029#define DSI_VLCCR_HLINE8_Pos (8U)
9030#define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos)
9031#define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
9032#define DSI_VLCCR_HLINE9_Pos (9U)
9033#define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos)
9034#define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
9035#define DSI_VLCCR_HLINE10_Pos (10U)
9036#define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos)
9037#define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
9038#define DSI_VLCCR_HLINE11_Pos (11U)
9039#define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos)
9040#define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
9041#define DSI_VLCCR_HLINE12_Pos (12U)
9042#define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos)
9043#define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
9044#define DSI_VLCCR_HLINE13_Pos (13U)
9045#define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos)
9046#define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
9047#define DSI_VLCCR_HLINE14_Pos (14U)
9048#define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos)
9049#define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
9050
9051/******************* Bit definition for DSI_VVSACCR register ***************/
9052#define DSI_VVSACCR_VSA_Pos (0U)
9053#define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos)
9054#define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk
9055#define DSI_VVSACCR_VSA0_Pos (0U)
9056#define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos)
9057#define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
9058#define DSI_VVSACCR_VSA1_Pos (1U)
9059#define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos)
9060#define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
9061#define DSI_VVSACCR_VSA2_Pos (2U)
9062#define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos)
9063#define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
9064#define DSI_VVSACCR_VSA3_Pos (3U)
9065#define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos)
9066#define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
9067#define DSI_VVSACCR_VSA4_Pos (4U)
9068#define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos)
9069#define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
9070#define DSI_VVSACCR_VSA5_Pos (5U)
9071#define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos)
9072#define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
9073#define DSI_VVSACCR_VSA6_Pos (6U)
9074#define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos)
9075#define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
9076#define DSI_VVSACCR_VSA7_Pos (7U)
9077#define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos)
9078#define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
9079#define DSI_VVSACCR_VSA8_Pos (8U)
9080#define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos)
9081#define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
9082#define DSI_VVSACCR_VSA9_Pos (9U)
9083#define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos)
9084#define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
9085
9086/******************* Bit definition for DSI_VVBPCCR register ************/
9087#define DSI_VVBPCCR_VBP_Pos (0U)
9088#define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos)
9089#define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk
9090#define DSI_VVBPCCR_VBP0_Pos (0U)
9091#define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos)
9092#define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
9093#define DSI_VVBPCCR_VBP1_Pos (1U)
9094#define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos)
9095#define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
9096#define DSI_VVBPCCR_VBP2_Pos (2U)
9097#define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos)
9098#define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
9099#define DSI_VVBPCCR_VBP3_Pos (3U)
9100#define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos)
9101#define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
9102#define DSI_VVBPCCR_VBP4_Pos (4U)
9103#define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos)
9104#define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
9105#define DSI_VVBPCCR_VBP5_Pos (5U)
9106#define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos)
9107#define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
9108#define DSI_VVBPCCR_VBP6_Pos (6U)
9109#define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos)
9110#define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
9111#define DSI_VVBPCCR_VBP7_Pos (7U)
9112#define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos)
9113#define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
9114#define DSI_VVBPCCR_VBP8_Pos (8U)
9115#define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos)
9116#define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
9117#define DSI_VVBPCCR_VBP9_Pos (9U)
9118#define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos)
9119#define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
9120
9121/******************* Bit definition for DSI_VVFPCCR register ************/
9122#define DSI_VVFPCCR_VFP_Pos (0U)
9123#define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos)
9124#define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk
9125#define DSI_VVFPCCR_VFP0_Pos (0U)
9126#define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos)
9127#define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
9128#define DSI_VVFPCCR_VFP1_Pos (1U)
9129#define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos)
9130#define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
9131#define DSI_VVFPCCR_VFP2_Pos (2U)
9132#define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos)
9133#define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
9134#define DSI_VVFPCCR_VFP3_Pos (3U)
9135#define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos)
9136#define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
9137#define DSI_VVFPCCR_VFP4_Pos (4U)
9138#define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos)
9139#define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
9140#define DSI_VVFPCCR_VFP5_Pos (5U)
9141#define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos)
9142#define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
9143#define DSI_VVFPCCR_VFP6_Pos (6U)
9144#define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos)
9145#define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
9146#define DSI_VVFPCCR_VFP7_Pos (7U)
9147#define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos)
9148#define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
9149#define DSI_VVFPCCR_VFP8_Pos (8U)
9150#define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos)
9151#define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
9152#define DSI_VVFPCCR_VFP9_Pos (9U)
9153#define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos)
9154#define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
9155
9156/******************* Bit definition for DSI_VVACCR register *************/
9157#define DSI_VVACCR_VA_Pos (0U)
9158#define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos)
9159#define DSI_VVACCR_VA DSI_VVACCR_VA_Msk
9160#define DSI_VVACCR_VA0_Pos (0U)
9161#define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos)
9162#define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
9163#define DSI_VVACCR_VA1_Pos (1U)
9164#define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos)
9165#define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
9166#define DSI_VVACCR_VA2_Pos (2U)
9167#define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos)
9168#define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
9169#define DSI_VVACCR_VA3_Pos (3U)
9170#define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos)
9171#define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
9172#define DSI_VVACCR_VA4_Pos (4U)
9173#define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos)
9174#define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
9175#define DSI_VVACCR_VA5_Pos (5U)
9176#define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos)
9177#define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
9178#define DSI_VVACCR_VA6_Pos (6U)
9179#define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos)
9180#define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
9181#define DSI_VVACCR_VA7_Pos (7U)
9182#define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos)
9183#define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
9184#define DSI_VVACCR_VA8_Pos (8U)
9185#define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos)
9186#define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
9187#define DSI_VVACCR_VA9_Pos (9U)
9188#define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos)
9189#define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
9190#define DSI_VVACCR_VA10_Pos (10U)
9191#define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos)
9192#define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
9193#define DSI_VVACCR_VA11_Pos (11U)
9194#define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos)
9195#define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
9196#define DSI_VVACCR_VA12_Pos (12U)
9197#define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos)
9198#define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
9199#define DSI_VVACCR_VA13_Pos (13U)
9200#define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos)
9201#define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
9202
9203/******************* Bit definition for DSI_TDCCR register **************/
9204#define DSI_TDCCR_3DM 0x00000003U
9205#define DSI_TDCCR_3DM0 0x00000001U
9206#define DSI_TDCCR_3DM1 0x00000002U
9207
9208#define DSI_TDCCR_3DF 0x0000000CU
9209#define DSI_TDCCR_3DF0 0x00000004U
9210#define DSI_TDCCR_3DF1 0x00000008U
9211
9212#define DSI_TDCCR_SVS_Pos (4U)
9213#define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos)
9214#define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk
9215#define DSI_TDCCR_RF_Pos (5U)
9216#define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos)
9217#define DSI_TDCCR_RF DSI_TDCCR_RF_Msk
9218#define DSI_TDCCR_S3DC_Pos (16U)
9219#define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos)
9220#define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk
9221
9222/******************* Bit definition for DSI_WCFGR register ***************/
9223#define DSI_WCFGR_DSIM_Pos (0U)
9224#define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos)
9225#define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk
9226#define DSI_WCFGR_COLMUX_Pos (1U)
9227#define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos)
9228#define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk
9229#define DSI_WCFGR_COLMUX0_Pos (1U)
9230#define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos)
9231#define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
9232#define DSI_WCFGR_COLMUX1_Pos (2U)
9233#define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos)
9234#define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
9235#define DSI_WCFGR_COLMUX2_Pos (3U)
9236#define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos)
9237#define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
9238
9239#define DSI_WCFGR_TESRC_Pos (4U)
9240#define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos)
9241#define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk
9242#define DSI_WCFGR_TEPOL_Pos (5U)
9243#define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos)
9244#define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk
9245#define DSI_WCFGR_AR_Pos (6U)
9246#define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos)
9247#define DSI_WCFGR_AR DSI_WCFGR_AR_Msk
9248#define DSI_WCFGR_VSPOL_Pos (7U)
9249#define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos)
9250#define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk
9251
9252/******************* Bit definition for DSI_WCR register *****************/
9253#define DSI_WCR_COLM_Pos (0U)
9254#define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos)
9255#define DSI_WCR_COLM DSI_WCR_COLM_Msk
9256#define DSI_WCR_SHTDN_Pos (1U)
9257#define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos)
9258#define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk
9259#define DSI_WCR_LTDCEN_Pos (2U)
9260#define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos)
9261#define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk
9262#define DSI_WCR_DSIEN_Pos (3U)
9263#define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos)
9264#define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk
9265
9266/******************* Bit definition for DSI_WIER register ****************/
9267#define DSI_WIER_TEIE_Pos (0U)
9268#define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos)
9269#define DSI_WIER_TEIE DSI_WIER_TEIE_Msk
9270#define DSI_WIER_ERIE_Pos (1U)
9271#define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos)
9272#define DSI_WIER_ERIE DSI_WIER_ERIE_Msk
9273#define DSI_WIER_PLLLIE_Pos (9U)
9274#define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos)
9275#define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk
9276#define DSI_WIER_PLLUIE_Pos (10U)
9277#define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos)
9278#define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk
9279#define DSI_WIER_RRIE_Pos (13U)
9280#define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos)
9281#define DSI_WIER_RRIE DSI_WIER_RRIE_Msk
9282
9283/******************* Bit definition for DSI_WISR register ****************/
9284#define DSI_WISR_TEIF_Pos (0U)
9285#define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos)
9286#define DSI_WISR_TEIF DSI_WISR_TEIF_Msk
9287#define DSI_WISR_ERIF_Pos (1U)
9288#define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos)
9289#define DSI_WISR_ERIF DSI_WISR_ERIF_Msk
9290#define DSI_WISR_BUSY_Pos (2U)
9291#define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos)
9292#define DSI_WISR_BUSY DSI_WISR_BUSY_Msk
9293#define DSI_WISR_PLLLS_Pos (8U)
9294#define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos)
9295#define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk
9296#define DSI_WISR_PLLLIF_Pos (9U)
9297#define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos)
9298#define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk
9299#define DSI_WISR_PLLUIF_Pos (10U)
9300#define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos)
9301#define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk
9302#define DSI_WISR_RRS_Pos (12U)
9303#define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos)
9304#define DSI_WISR_RRS DSI_WISR_RRS_Msk
9305#define DSI_WISR_RRIF_Pos (13U)
9306#define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos)
9307#define DSI_WISR_RRIF DSI_WISR_RRIF_Msk
9308
9309/******************* Bit definition for DSI_WIFCR register ***************/
9310#define DSI_WIFCR_CTEIF_Pos (0U)
9311#define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos)
9312#define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk
9313#define DSI_WIFCR_CERIF_Pos (1U)
9314#define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos)
9315#define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk
9316#define DSI_WIFCR_CPLLLIF_Pos (9U)
9317#define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos)
9318#define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk
9319#define DSI_WIFCR_CPLLUIF_Pos (10U)
9320#define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos)
9321#define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk
9322#define DSI_WIFCR_CRRIF_Pos (13U)
9323#define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos)
9324#define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk
9325
9326/******************* Bit definition for DSI_WPCR0 register ***************/
9327#define DSI_WPCR0_UIX4_Pos (0U)
9328#define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos)
9329#define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk
9330#define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos)
9331#define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos)
9332#define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos)
9333#define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos)
9334#define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos)
9335#define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos)
9336
9337#define DSI_WPCR0_SWCL_Pos (6U)
9338#define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos)
9339#define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk
9340#define DSI_WPCR0_SWDL0_Pos (7U)
9341#define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos)
9342#define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk
9343#define DSI_WPCR0_SWDL1_Pos (8U)
9344#define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos)
9345#define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk
9346#define DSI_WPCR0_HSICL_Pos (9U)
9347#define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos)
9348#define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk
9349#define DSI_WPCR0_HSIDL0_Pos (10U)
9350#define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos)
9351#define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk
9352#define DSI_WPCR0_HSIDL1_Pos (11U)
9353#define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos)
9354#define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk
9355#define DSI_WPCR0_FTXSMCL_Pos (12U)
9356#define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos)
9357#define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk
9358#define DSI_WPCR0_FTXSMDL_Pos (13U)
9359#define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos)
9360#define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk
9361#define DSI_WPCR0_CDOFFDL_Pos (14U)
9362#define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos)
9363#define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk
9364#define DSI_WPCR0_TDDL_Pos (16U)
9365#define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos)
9366#define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk
9367#define DSI_WPCR0_PDEN_Pos (18U)
9368#define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos)
9369#define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk
9370#define DSI_WPCR0_TCLKPREPEN_Pos (19U)
9371#define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)
9372#define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk
9373#define DSI_WPCR0_TCLKZEROEN_Pos (20U)
9374#define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)
9375#define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk
9376#define DSI_WPCR0_THSPREPEN_Pos (21U)
9377#define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos)
9378#define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk
9379#define DSI_WPCR0_THSTRAILEN_Pos (22U)
9380#define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)
9381#define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk
9382#define DSI_WPCR0_THSZEROEN_Pos (23U)
9383#define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos)
9384#define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk
9385#define DSI_WPCR0_TLPXDEN_Pos (24U)
9386#define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos)
9387#define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk
9388#define DSI_WPCR0_THSEXITEN_Pos (25U)
9389#define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos)
9390#define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk
9391#define DSI_WPCR0_TLPXCEN_Pos (26U)
9392#define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos)
9393#define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk
9394#define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
9395#define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)
9396#define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk
9397
9398/******************* Bit definition for DSI_WPCR1 register ***************/
9399#define DSI_WPCR1_HSTXDCL_Pos (0U)
9400#define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos)
9401#define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk
9402#define DSI_WPCR1_HSTXDCL0_Pos (0U)
9403#define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)
9404#define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
9405#define DSI_WPCR1_HSTXDCL1_Pos (1U)
9406#define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)
9407#define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
9408
9409#define DSI_WPCR1_HSTXDDL_Pos (2U)
9410#define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos)
9411#define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk
9412#define DSI_WPCR1_HSTXDDL0_Pos (2U)
9413#define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)
9414#define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
9415#define DSI_WPCR1_HSTXDDL1_Pos (3U)
9416#define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)
9417#define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
9418
9419#define DSI_WPCR1_LPSRCCL_Pos (6U)
9420#define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos)
9421#define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk
9422#define DSI_WPCR1_LPSRCCL0_Pos (6U)
9423#define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)
9424#define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
9425#define DSI_WPCR1_LPSRCCL1_Pos (7U)
9426#define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)
9427#define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
9428
9429#define DSI_WPCR1_LPSRCDL_Pos (8U)
9430#define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos)
9431#define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk
9432#define DSI_WPCR1_LPSRCDL0_Pos (8U)
9433#define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)
9434#define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
9435#define DSI_WPCR1_LPSRCDL1_Pos (9U)
9436#define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)
9437#define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
9438
9439#define DSI_WPCR1_SDDC_Pos (12U)
9440#define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos)
9441#define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk
9442
9443#define DSI_WPCR1_LPRXVCDL_Pos (14U)
9444#define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)
9445#define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk
9446#define DSI_WPCR1_LPRXVCDL0_Pos (14U)
9447#define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)
9448#define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
9449#define DSI_WPCR1_LPRXVCDL1_Pos (15U)
9450#define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)
9451#define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
9452
9453#define DSI_WPCR1_HSTXSRCCL_Pos (16U)
9454#define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)
9455#define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk
9456#define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
9457#define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)
9458#define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
9459#define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
9460#define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)
9461#define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
9462
9463#define DSI_WPCR1_HSTXSRCDL_Pos (18U)
9464#define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)
9465#define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk
9466#define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
9467#define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)
9468#define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
9469#define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
9470#define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)
9471#define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
9472
9473#define DSI_WPCR1_FLPRXLPM_Pos (22U)
9474#define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)
9475#define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk
9476
9477#define DSI_WPCR1_LPRXFT_Pos (25U)
9478#define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos)
9479#define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk
9480#define DSI_WPCR1_LPRXFT0_Pos (25U)
9481#define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos)
9482#define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
9483#define DSI_WPCR1_LPRXFT1_Pos (26U)
9484#define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos)
9485#define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
9486
9487/******************* Bit definition for DSI_WPCR2 register ***************/
9488#define DSI_WPCR2_TCLKPREP_Pos (0U)
9489#define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)
9490#define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk
9491#define DSI_WPCR2_TCLKPREP0_Pos (0U)
9492#define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)
9493#define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
9494#define DSI_WPCR2_TCLKPREP1_Pos (1U)
9495#define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)
9496#define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
9497#define DSI_WPCR2_TCLKPREP2_Pos (2U)
9498#define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)
9499#define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
9500#define DSI_WPCR2_TCLKPREP3_Pos (3U)
9501#define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)
9502#define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
9503#define DSI_WPCR2_TCLKPREP4_Pos (4U)
9504#define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)
9505#define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
9506#define DSI_WPCR2_TCLKPREP5_Pos (5U)
9507#define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)
9508#define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
9509#define DSI_WPCR2_TCLKPREP6_Pos (6U)
9510#define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)
9511#define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
9512#define DSI_WPCR2_TCLKPREP7_Pos (7U)
9513#define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)
9514#define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
9515
9516#define DSI_WPCR2_TCLKZERO_Pos (8U)
9517#define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)
9518#define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk
9519#define DSI_WPCR2_TCLKZERO0_Pos (8U)
9520#define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)
9521#define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
9522#define DSI_WPCR2_TCLKZERO1_Pos (9U)
9523#define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)
9524#define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
9525#define DSI_WPCR2_TCLKZERO2_Pos (10U)
9526#define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)
9527#define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
9528#define DSI_WPCR2_TCLKZERO3_Pos (11U)
9529#define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)
9530#define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
9531#define DSI_WPCR2_TCLKZERO4_Pos (12U)
9532#define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)
9533#define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
9534#define DSI_WPCR2_TCLKZERO5_Pos (13U)
9535#define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)
9536#define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
9537#define DSI_WPCR2_TCLKZERO6_Pos (14U)
9538#define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)
9539#define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
9540#define DSI_WPCR2_TCLKZERO7_Pos (15U)
9541#define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)
9542#define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
9543
9544#define DSI_WPCR2_THSPREP_Pos (16U)
9545#define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos)
9546#define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk
9547#define DSI_WPCR2_THSPREP0_Pos (16U)
9548#define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos)
9549#define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
9550#define DSI_WPCR2_THSPREP1_Pos (17U)
9551#define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos)
9552#define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
9553#define DSI_WPCR2_THSPREP2_Pos (18U)
9554#define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos)
9555#define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
9556#define DSI_WPCR2_THSPREP3_Pos (19U)
9557#define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos)
9558#define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
9559#define DSI_WPCR2_THSPREP4_Pos (20U)
9560#define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos)
9561#define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
9562#define DSI_WPCR2_THSPREP5_Pos (21U)
9563#define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos)
9564#define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
9565#define DSI_WPCR2_THSPREP6_Pos (22U)
9566#define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos)
9567#define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
9568#define DSI_WPCR2_THSPREP7_Pos (23U)
9569#define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos)
9570#define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
9571
9572#define DSI_WPCR2_THSTRAIL_Pos (24U)
9573#define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)
9574#define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk
9575#define DSI_WPCR2_THSTRAIL0_Pos (24U)
9576#define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)
9577#define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
9578#define DSI_WPCR2_THSTRAIL1_Pos (25U)
9579#define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)
9580#define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
9581#define DSI_WPCR2_THSTRAIL2_Pos (26U)
9582#define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)
9583#define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
9584#define DSI_WPCR2_THSTRAIL3_Pos (27U)
9585#define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)
9586#define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
9587#define DSI_WPCR2_THSTRAIL4_Pos (28U)
9588#define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)
9589#define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
9590#define DSI_WPCR2_THSTRAIL5_Pos (29U)
9591#define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)
9592#define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
9593#define DSI_WPCR2_THSTRAIL6_Pos (30U)
9594#define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)
9595#define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
9596#define DSI_WPCR2_THSTRAIL7_Pos (31U)
9597#define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)
9598#define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
9599
9600/******************* Bit definition for DSI_WPCR3 register ***************/
9601#define DSI_WPCR3_THSZERO_Pos (0U)
9602#define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos)
9603#define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk
9604#define DSI_WPCR3_THSZERO0_Pos (0U)
9605#define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos)
9606#define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
9607#define DSI_WPCR3_THSZERO1_Pos (1U)
9608#define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos)
9609#define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
9610#define DSI_WPCR3_THSZERO2_Pos (2U)
9611#define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos)
9612#define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
9613#define DSI_WPCR3_THSZERO3_Pos (3U)
9614#define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos)
9615#define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
9616#define DSI_WPCR3_THSZERO4_Pos (4U)
9617#define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos)
9618#define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
9619#define DSI_WPCR3_THSZERO5_Pos (5U)
9620#define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos)
9621#define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
9622#define DSI_WPCR3_THSZERO6_Pos (6U)
9623#define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos)
9624#define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
9625#define DSI_WPCR3_THSZERO7_Pos (7U)
9626#define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos)
9627#define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
9628
9629#define DSI_WPCR3_TLPXD_Pos (8U)
9630#define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos)
9631#define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk
9632#define DSI_WPCR3_TLPXD0_Pos (8U)
9633#define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos)
9634#define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
9635#define DSI_WPCR3_TLPXD1_Pos (9U)
9636#define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos)
9637#define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
9638#define DSI_WPCR3_TLPXD2_Pos (10U)
9639#define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos)
9640#define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
9641#define DSI_WPCR3_TLPXD3_Pos (11U)
9642#define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos)
9643#define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
9644#define DSI_WPCR3_TLPXD4_Pos (12U)
9645#define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos)
9646#define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
9647#define DSI_WPCR3_TLPXD5_Pos (13U)
9648#define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos)
9649#define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
9650#define DSI_WPCR3_TLPXD6_Pos (14U)
9651#define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos)
9652#define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
9653#define DSI_WPCR3_TLPXD7_Pos (15U)
9654#define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos)
9655#define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
9656
9657#define DSI_WPCR3_THSEXIT_Pos (16U)
9658#define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos)
9659#define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk
9660#define DSI_WPCR3_THSEXIT0_Pos (16U)
9661#define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos)
9662#define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
9663#define DSI_WPCR3_THSEXIT1_Pos (17U)
9664#define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos)
9665#define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
9666#define DSI_WPCR3_THSEXIT2_Pos (18U)
9667#define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos)
9668#define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
9669#define DSI_WPCR3_THSEXIT3_Pos (19U)
9670#define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos)
9671#define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
9672#define DSI_WPCR3_THSEXIT4_Pos (20U)
9673#define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos)
9674#define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
9675#define DSI_WPCR3_THSEXIT5_Pos (21U)
9676#define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos)
9677#define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
9678#define DSI_WPCR3_THSEXIT6_Pos (22U)
9679#define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos)
9680#define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
9681#define DSI_WPCR3_THSEXIT7_Pos (23U)
9682#define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos)
9683#define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
9684
9685#define DSI_WPCR3_TLPXC_Pos (24U)
9686#define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos)
9687#define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk
9688#define DSI_WPCR3_TLPXC0_Pos (24U)
9689#define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos)
9690#define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
9691#define DSI_WPCR3_TLPXC1_Pos (25U)
9692#define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos)
9693#define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
9694#define DSI_WPCR3_TLPXC2_Pos (26U)
9695#define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos)
9696#define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
9697#define DSI_WPCR3_TLPXC3_Pos (27U)
9698#define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos)
9699#define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
9700#define DSI_WPCR3_TLPXC4_Pos (28U)
9701#define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos)
9702#define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
9703#define DSI_WPCR3_TLPXC5_Pos (29U)
9704#define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos)
9705#define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
9706#define DSI_WPCR3_TLPXC6_Pos (30U)
9707#define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos)
9708#define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
9709#define DSI_WPCR3_TLPXC7_Pos (31U)
9710#define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos)
9711#define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
9712
9713/******************* Bit definition for DSI_WPCR4 register ***************/
9714#define DSI_WPCR4_TCLKPOST_Pos (0U)
9715#define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)
9716#define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk
9717#define DSI_WPCR4_TCLKPOST0_Pos (0U)
9718#define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)
9719#define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
9720#define DSI_WPCR4_TCLKPOST1_Pos (1U)
9721#define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)
9722#define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
9723#define DSI_WPCR4_TCLKPOST2_Pos (2U)
9724#define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)
9725#define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
9726#define DSI_WPCR4_TCLKPOST3_Pos (3U)
9727#define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)
9728#define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
9729#define DSI_WPCR4_TCLKPOST4_Pos (4U)
9730#define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)
9731#define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
9732#define DSI_WPCR4_TCLKPOST5_Pos (5U)
9733#define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)
9734#define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
9735#define DSI_WPCR4_TCLKPOST6_Pos (6U)
9736#define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)
9737#define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
9738#define DSI_WPCR4_TCLKPOST7_Pos (7U)
9739#define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)
9740#define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
9741
9742/******************* Bit definition for DSI_WRPCR register ***************/
9743#define DSI_WRPCR_PLLEN_Pos (0U)
9744#define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos)
9745#define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk
9746#define DSI_WRPCR_PLL_NDIV_Pos (2U)
9747#define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)
9748#define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk
9749#define DSI_WRPCR_PLL_NDIV0_Pos (2U)
9750#define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)
9751#define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
9752#define DSI_WRPCR_PLL_NDIV1_Pos (3U)
9753#define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)
9754#define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
9755#define DSI_WRPCR_PLL_NDIV2_Pos (4U)
9756#define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)
9757#define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
9758#define DSI_WRPCR_PLL_NDIV3_Pos (5U)
9759#define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)
9760#define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
9761#define DSI_WRPCR_PLL_NDIV4_Pos (6U)
9762#define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)
9763#define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
9764#define DSI_WRPCR_PLL_NDIV5_Pos (7U)
9765#define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)
9766#define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
9767#define DSI_WRPCR_PLL_NDIV6_Pos (8U)
9768#define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)
9769#define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
9770
9771#define DSI_WRPCR_PLL_IDF_Pos (11U)
9772#define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos)
9773#define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk
9774#define DSI_WRPCR_PLL_IDF0_Pos (11U)
9775#define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)
9776#define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
9777#define DSI_WRPCR_PLL_IDF1_Pos (12U)
9778#define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)
9779#define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
9780#define DSI_WRPCR_PLL_IDF2_Pos (13U)
9781#define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)
9782#define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
9783#define DSI_WRPCR_PLL_IDF3_Pos (14U)
9784#define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)
9785#define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
9786
9787#define DSI_WRPCR_PLL_ODF_Pos (16U)
9788#define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos)
9789#define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk
9790#define DSI_WRPCR_PLL_ODF0_Pos (16U)
9791#define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)
9792#define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
9793#define DSI_WRPCR_PLL_ODF1_Pos (17U)
9794#define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)
9795#define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
9796
9797#define DSI_WRPCR_REGEN_Pos (24U)
9798#define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos)
9799#define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk
9800
9801/******************************************************************************/
9802/* */
9803/* External Interrupt/Event Controller */
9804/* */
9805/******************************************************************************/
9806/******************* Bit definition for EXTI_IMR register *******************/
9807#define EXTI_IMR_MR0_Pos (0U)
9808#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
9809#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
9810#define EXTI_IMR_MR1_Pos (1U)
9811#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
9812#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
9813#define EXTI_IMR_MR2_Pos (2U)
9814#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
9815#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
9816#define EXTI_IMR_MR3_Pos (3U)
9817#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
9818#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
9819#define EXTI_IMR_MR4_Pos (4U)
9820#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
9821#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
9822#define EXTI_IMR_MR5_Pos (5U)
9823#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
9824#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
9825#define EXTI_IMR_MR6_Pos (6U)
9826#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
9827#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
9828#define EXTI_IMR_MR7_Pos (7U)
9829#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
9830#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
9831#define EXTI_IMR_MR8_Pos (8U)
9832#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
9833#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
9834#define EXTI_IMR_MR9_Pos (9U)
9835#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
9836#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
9837#define EXTI_IMR_MR10_Pos (10U)
9838#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
9839#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
9840#define EXTI_IMR_MR11_Pos (11U)
9841#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
9842#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
9843#define EXTI_IMR_MR12_Pos (12U)
9844#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
9845#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
9846#define EXTI_IMR_MR13_Pos (13U)
9847#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
9848#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
9849#define EXTI_IMR_MR14_Pos (14U)
9850#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
9851#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
9852#define EXTI_IMR_MR15_Pos (15U)
9853#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
9854#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
9855#define EXTI_IMR_MR16_Pos (16U)
9856#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
9857#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
9858#define EXTI_IMR_MR17_Pos (17U)
9859#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
9860#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
9861#define EXTI_IMR_MR18_Pos (18U)
9862#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
9863#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
9864#define EXTI_IMR_MR19_Pos (19U)
9865#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
9866#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
9867#define EXTI_IMR_MR20_Pos (20U)
9868#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
9869#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
9870#define EXTI_IMR_MR21_Pos (21U)
9871#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
9872#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
9873#define EXTI_IMR_MR22_Pos (22U)
9874#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
9875#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
9876
9877/* Reference Defines */
9878#define EXTI_IMR_IM0 EXTI_IMR_MR0
9879#define EXTI_IMR_IM1 EXTI_IMR_MR1
9880#define EXTI_IMR_IM2 EXTI_IMR_MR2
9881#define EXTI_IMR_IM3 EXTI_IMR_MR3
9882#define EXTI_IMR_IM4 EXTI_IMR_MR4
9883#define EXTI_IMR_IM5 EXTI_IMR_MR5
9884#define EXTI_IMR_IM6 EXTI_IMR_MR6
9885#define EXTI_IMR_IM7 EXTI_IMR_MR7
9886#define EXTI_IMR_IM8 EXTI_IMR_MR8
9887#define EXTI_IMR_IM9 EXTI_IMR_MR9
9888#define EXTI_IMR_IM10 EXTI_IMR_MR10
9889#define EXTI_IMR_IM11 EXTI_IMR_MR11
9890#define EXTI_IMR_IM12 EXTI_IMR_MR12
9891#define EXTI_IMR_IM13 EXTI_IMR_MR13
9892#define EXTI_IMR_IM14 EXTI_IMR_MR14
9893#define EXTI_IMR_IM15 EXTI_IMR_MR15
9894#define EXTI_IMR_IM16 EXTI_IMR_MR16
9895#define EXTI_IMR_IM17 EXTI_IMR_MR17
9896#define EXTI_IMR_IM18 EXTI_IMR_MR18
9897#define EXTI_IMR_IM19 EXTI_IMR_MR19
9898#define EXTI_IMR_IM20 EXTI_IMR_MR20
9899#define EXTI_IMR_IM21 EXTI_IMR_MR21
9900#define EXTI_IMR_IM22 EXTI_IMR_MR22
9901#define EXTI_IMR_IM_Pos (0U)
9902#define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
9903#define EXTI_IMR_IM EXTI_IMR_IM_Msk
9904
9905/******************* Bit definition for EXTI_EMR register *******************/
9906#define EXTI_EMR_MR0_Pos (0U)
9907#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
9908#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
9909#define EXTI_EMR_MR1_Pos (1U)
9910#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
9911#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
9912#define EXTI_EMR_MR2_Pos (2U)
9913#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
9914#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
9915#define EXTI_EMR_MR3_Pos (3U)
9916#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
9917#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
9918#define EXTI_EMR_MR4_Pos (4U)
9919#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
9920#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
9921#define EXTI_EMR_MR5_Pos (5U)
9922#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
9923#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
9924#define EXTI_EMR_MR6_Pos (6U)
9925#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
9926#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
9927#define EXTI_EMR_MR7_Pos (7U)
9928#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
9929#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
9930#define EXTI_EMR_MR8_Pos (8U)
9931#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
9932#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
9933#define EXTI_EMR_MR9_Pos (9U)
9934#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
9935#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
9936#define EXTI_EMR_MR10_Pos (10U)
9937#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
9938#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
9939#define EXTI_EMR_MR11_Pos (11U)
9940#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
9941#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
9942#define EXTI_EMR_MR12_Pos (12U)
9943#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
9944#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
9945#define EXTI_EMR_MR13_Pos (13U)
9946#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
9947#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
9948#define EXTI_EMR_MR14_Pos (14U)
9949#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
9950#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
9951#define EXTI_EMR_MR15_Pos (15U)
9952#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
9953#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
9954#define EXTI_EMR_MR16_Pos (16U)
9955#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
9956#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
9957#define EXTI_EMR_MR17_Pos (17U)
9958#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
9959#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
9960#define EXTI_EMR_MR18_Pos (18U)
9961#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
9962#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
9963#define EXTI_EMR_MR19_Pos (19U)
9964#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
9965#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
9966#define EXTI_EMR_MR20_Pos (20U)
9967#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
9968#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
9969#define EXTI_EMR_MR21_Pos (21U)
9970#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
9971#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
9972#define EXTI_EMR_MR22_Pos (22U)
9973#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
9974#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
9975
9976/* Reference Defines */
9977#define EXTI_EMR_EM0 EXTI_EMR_MR0
9978#define EXTI_EMR_EM1 EXTI_EMR_MR1
9979#define EXTI_EMR_EM2 EXTI_EMR_MR2
9980#define EXTI_EMR_EM3 EXTI_EMR_MR3
9981#define EXTI_EMR_EM4 EXTI_EMR_MR4
9982#define EXTI_EMR_EM5 EXTI_EMR_MR5
9983#define EXTI_EMR_EM6 EXTI_EMR_MR6
9984#define EXTI_EMR_EM7 EXTI_EMR_MR7
9985#define EXTI_EMR_EM8 EXTI_EMR_MR8
9986#define EXTI_EMR_EM9 EXTI_EMR_MR9
9987#define EXTI_EMR_EM10 EXTI_EMR_MR10
9988#define EXTI_EMR_EM11 EXTI_EMR_MR11
9989#define EXTI_EMR_EM12 EXTI_EMR_MR12
9990#define EXTI_EMR_EM13 EXTI_EMR_MR13
9991#define EXTI_EMR_EM14 EXTI_EMR_MR14
9992#define EXTI_EMR_EM15 EXTI_EMR_MR15
9993#define EXTI_EMR_EM16 EXTI_EMR_MR16
9994#define EXTI_EMR_EM17 EXTI_EMR_MR17
9995#define EXTI_EMR_EM18 EXTI_EMR_MR18
9996#define EXTI_EMR_EM19 EXTI_EMR_MR19
9997#define EXTI_EMR_EM20 EXTI_EMR_MR20
9998#define EXTI_EMR_EM21 EXTI_EMR_MR21
9999#define EXTI_EMR_EM22 EXTI_EMR_MR22
10000
10001/****************** Bit definition for EXTI_RTSR register *******************/
10002#define EXTI_RTSR_TR0_Pos (0U)
10003#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
10004#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
10005#define EXTI_RTSR_TR1_Pos (1U)
10006#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
10007#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
10008#define EXTI_RTSR_TR2_Pos (2U)
10009#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
10010#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
10011#define EXTI_RTSR_TR3_Pos (3U)
10012#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
10013#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
10014#define EXTI_RTSR_TR4_Pos (4U)
10015#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
10016#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
10017#define EXTI_RTSR_TR5_Pos (5U)
10018#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
10019#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
10020#define EXTI_RTSR_TR6_Pos (6U)
10021#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
10022#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
10023#define EXTI_RTSR_TR7_Pos (7U)
10024#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
10025#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
10026#define EXTI_RTSR_TR8_Pos (8U)
10027#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
10028#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
10029#define EXTI_RTSR_TR9_Pos (9U)
10030#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
10031#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
10032#define EXTI_RTSR_TR10_Pos (10U)
10033#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
10034#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
10035#define EXTI_RTSR_TR11_Pos (11U)
10036#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
10037#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
10038#define EXTI_RTSR_TR12_Pos (12U)
10039#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
10040#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
10041#define EXTI_RTSR_TR13_Pos (13U)
10042#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
10043#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
10044#define EXTI_RTSR_TR14_Pos (14U)
10045#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
10046#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
10047#define EXTI_RTSR_TR15_Pos (15U)
10048#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
10049#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
10050#define EXTI_RTSR_TR16_Pos (16U)
10051#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
10052#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
10053#define EXTI_RTSR_TR17_Pos (17U)
10054#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
10055#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
10056#define EXTI_RTSR_TR18_Pos (18U)
10057#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
10058#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
10059#define EXTI_RTSR_TR19_Pos (19U)
10060#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
10061#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
10062#define EXTI_RTSR_TR20_Pos (20U)
10063#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
10064#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
10065#define EXTI_RTSR_TR21_Pos (21U)
10066#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
10067#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
10068#define EXTI_RTSR_TR22_Pos (22U)
10069#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
10070#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
10071
10072/****************** Bit definition for EXTI_FTSR register *******************/
10073#define EXTI_FTSR_TR0_Pos (0U)
10074#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
10075#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
10076#define EXTI_FTSR_TR1_Pos (1U)
10077#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
10078#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
10079#define EXTI_FTSR_TR2_Pos (2U)
10080#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
10081#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
10082#define EXTI_FTSR_TR3_Pos (3U)
10083#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
10084#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
10085#define EXTI_FTSR_TR4_Pos (4U)
10086#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
10087#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
10088#define EXTI_FTSR_TR5_Pos (5U)
10089#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
10090#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
10091#define EXTI_FTSR_TR6_Pos (6U)
10092#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
10093#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
10094#define EXTI_FTSR_TR7_Pos (7U)
10095#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
10096#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
10097#define EXTI_FTSR_TR8_Pos (8U)
10098#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
10099#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
10100#define EXTI_FTSR_TR9_Pos (9U)
10101#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
10102#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
10103#define EXTI_FTSR_TR10_Pos (10U)
10104#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
10105#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
10106#define EXTI_FTSR_TR11_Pos (11U)
10107#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
10108#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
10109#define EXTI_FTSR_TR12_Pos (12U)
10110#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
10111#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
10112#define EXTI_FTSR_TR13_Pos (13U)
10113#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
10114#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
10115#define EXTI_FTSR_TR14_Pos (14U)
10116#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
10117#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
10118#define EXTI_FTSR_TR15_Pos (15U)
10119#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
10120#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
10121#define EXTI_FTSR_TR16_Pos (16U)
10122#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
10123#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
10124#define EXTI_FTSR_TR17_Pos (17U)
10125#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
10126#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
10127#define EXTI_FTSR_TR18_Pos (18U)
10128#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
10129#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
10130#define EXTI_FTSR_TR19_Pos (19U)
10131#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
10132#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
10133#define EXTI_FTSR_TR20_Pos (20U)
10134#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
10135#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
10136#define EXTI_FTSR_TR21_Pos (21U)
10137#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
10138#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
10139#define EXTI_FTSR_TR22_Pos (22U)
10140#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
10141#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
10142
10143/****************** Bit definition for EXTI_SWIER register ******************/
10144#define EXTI_SWIER_SWIER0_Pos (0U)
10145#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
10146#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
10147#define EXTI_SWIER_SWIER1_Pos (1U)
10148#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
10149#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
10150#define EXTI_SWIER_SWIER2_Pos (2U)
10151#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
10152#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
10153#define EXTI_SWIER_SWIER3_Pos (3U)
10154#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
10155#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
10156#define EXTI_SWIER_SWIER4_Pos (4U)
10157#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
10158#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
10159#define EXTI_SWIER_SWIER5_Pos (5U)
10160#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
10161#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
10162#define EXTI_SWIER_SWIER6_Pos (6U)
10163#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
10164#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
10165#define EXTI_SWIER_SWIER7_Pos (7U)
10166#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
10167#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
10168#define EXTI_SWIER_SWIER8_Pos (8U)
10169#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
10170#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
10171#define EXTI_SWIER_SWIER9_Pos (9U)
10172#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
10173#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
10174#define EXTI_SWIER_SWIER10_Pos (10U)
10175#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
10176#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
10177#define EXTI_SWIER_SWIER11_Pos (11U)
10178#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
10179#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
10180#define EXTI_SWIER_SWIER12_Pos (12U)
10181#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
10182#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
10183#define EXTI_SWIER_SWIER13_Pos (13U)
10184#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
10185#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
10186#define EXTI_SWIER_SWIER14_Pos (14U)
10187#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
10188#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
10189#define EXTI_SWIER_SWIER15_Pos (15U)
10190#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
10191#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
10192#define EXTI_SWIER_SWIER16_Pos (16U)
10193#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
10194#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
10195#define EXTI_SWIER_SWIER17_Pos (17U)
10196#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
10197#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
10198#define EXTI_SWIER_SWIER18_Pos (18U)
10199#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
10200#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
10201#define EXTI_SWIER_SWIER19_Pos (19U)
10202#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
10203#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
10204#define EXTI_SWIER_SWIER20_Pos (20U)
10205#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
10206#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
10207#define EXTI_SWIER_SWIER21_Pos (21U)
10208#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
10209#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
10210#define EXTI_SWIER_SWIER22_Pos (22U)
10211#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
10212#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
10213
10214/******************* Bit definition for EXTI_PR register ********************/
10215#define EXTI_PR_PR0_Pos (0U)
10216#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
10217#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
10218#define EXTI_PR_PR1_Pos (1U)
10219#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
10220#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
10221#define EXTI_PR_PR2_Pos (2U)
10222#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
10223#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
10224#define EXTI_PR_PR3_Pos (3U)
10225#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
10226#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
10227#define EXTI_PR_PR4_Pos (4U)
10228#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
10229#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
10230#define EXTI_PR_PR5_Pos (5U)
10231#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
10232#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
10233#define EXTI_PR_PR6_Pos (6U)
10234#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
10235#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
10236#define EXTI_PR_PR7_Pos (7U)
10237#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
10238#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
10239#define EXTI_PR_PR8_Pos (8U)
10240#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
10241#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
10242#define EXTI_PR_PR9_Pos (9U)
10243#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
10244#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
10245#define EXTI_PR_PR10_Pos (10U)
10246#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
10247#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
10248#define EXTI_PR_PR11_Pos (11U)
10249#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
10250#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
10251#define EXTI_PR_PR12_Pos (12U)
10252#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
10253#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
10254#define EXTI_PR_PR13_Pos (13U)
10255#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
10256#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
10257#define EXTI_PR_PR14_Pos (14U)
10258#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
10259#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
10260#define EXTI_PR_PR15_Pos (15U)
10261#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
10262#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
10263#define EXTI_PR_PR16_Pos (16U)
10264#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
10265#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
10266#define EXTI_PR_PR17_Pos (17U)
10267#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
10268#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
10269#define EXTI_PR_PR18_Pos (18U)
10270#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
10271#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
10272#define EXTI_PR_PR19_Pos (19U)
10273#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
10274#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
10275#define EXTI_PR_PR20_Pos (20U)
10276#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
10277#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
10278#define EXTI_PR_PR21_Pos (21U)
10279#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
10280#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
10281#define EXTI_PR_PR22_Pos (22U)
10282#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
10283#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
10284
10285/******************************************************************************/
10286/* */
10287/* FLASH */
10288/* */
10289/******************************************************************************/
10290/******************* Bits definition for FLASH_ACR register *****************/
10291#define FLASH_ACR_LATENCY_Pos (0U)
10292#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
10293#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10294#define FLASH_ACR_LATENCY_0WS 0x00000000U
10295#define FLASH_ACR_LATENCY_1WS 0x00000001U
10296#define FLASH_ACR_LATENCY_2WS 0x00000002U
10297#define FLASH_ACR_LATENCY_3WS 0x00000003U
10298#define FLASH_ACR_LATENCY_4WS 0x00000004U
10299#define FLASH_ACR_LATENCY_5WS 0x00000005U
10300#define FLASH_ACR_LATENCY_6WS 0x00000006U
10301#define FLASH_ACR_LATENCY_7WS 0x00000007U
10302
10303#define FLASH_ACR_LATENCY_8WS 0x00000008U
10304#define FLASH_ACR_LATENCY_9WS 0x00000009U
10305#define FLASH_ACR_LATENCY_10WS 0x0000000AU
10306#define FLASH_ACR_LATENCY_11WS 0x0000000BU
10307#define FLASH_ACR_LATENCY_12WS 0x0000000CU
10308#define FLASH_ACR_LATENCY_13WS 0x0000000DU
10309#define FLASH_ACR_LATENCY_14WS 0x0000000EU
10310#define FLASH_ACR_LATENCY_15WS 0x0000000FU
10311
10312#define FLASH_ACR_PRFTEN_Pos (8U)
10313#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
10314#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
10315#define FLASH_ACR_ICEN_Pos (9U)
10316#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
10317#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
10318#define FLASH_ACR_DCEN_Pos (10U)
10319#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
10320#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
10321#define FLASH_ACR_ICRST_Pos (11U)
10322#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
10323#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
10324#define FLASH_ACR_DCRST_Pos (12U)
10325#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
10326#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
10327
10328/******************* Bits definition for FLASH_SR register ******************/
10329#define FLASH_SR_EOP_Pos (0U)
10330#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
10331#define FLASH_SR_EOP FLASH_SR_EOP_Msk
10332#define FLASH_SR_OPERR_Pos (1U)
10333#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
10334#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
10335#define FLASH_SR_WRPERR_Pos (4U)
10336#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
10337#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10338#define FLASH_SR_PGAERR_Pos (5U)
10339#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
10340#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
10341#define FLASH_SR_PGPERR_Pos (6U)
10342#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
10343#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
10344#define FLASH_SR_PGSERR_Pos (7U)
10345#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
10346#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10347#define FLASH_SR_RDERR_Pos (8U)
10348#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
10349#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
10350#define FLASH_SR_BSY_Pos (16U)
10351#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
10352#define FLASH_SR_BSY FLASH_SR_BSY_Msk
10353
10354/******************* Bits definition for FLASH_CR register ******************/
10355#define FLASH_CR_PG_Pos (0U)
10356#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
10357#define FLASH_CR_PG FLASH_CR_PG_Msk
10358#define FLASH_CR_SER_Pos (1U)
10359#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
10360#define FLASH_CR_SER FLASH_CR_SER_Msk
10361#define FLASH_CR_MER_Pos (2U)
10362#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
10363#define FLASH_CR_MER FLASH_CR_MER_Msk
10364#define FLASH_CR_MER1 FLASH_CR_MER
10365#define FLASH_CR_SNB_Pos (3U)
10366#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
10367#define FLASH_CR_SNB FLASH_CR_SNB_Msk
10368#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
10369#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
10370#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
10371#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
10372#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
10373#define FLASH_CR_PSIZE_Pos (8U)
10374#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
10375#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10376#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
10377#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
10378#define FLASH_CR_MER2_Pos (15U)
10379#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos)
10380#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
10381#define FLASH_CR_STRT_Pos (16U)
10382#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
10383#define FLASH_CR_STRT FLASH_CR_STRT_Msk
10384#define FLASH_CR_EOPIE_Pos (24U)
10385#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
10386#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10387#define FLASH_CR_ERRIE_Pos (25U)
10388#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
10389#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
10390#define FLASH_CR_LOCK_Pos (31U)
10391#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
10392#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10393
10394/******************* Bits definition for FLASH_OPTCR register ***************/
10395#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10396#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
10397#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10398#define FLASH_OPTCR_OPTSTRT_Pos (1U)
10399#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
10400#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
10401
10402#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
10403#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
10404#define FLASH_OPTCR_BOR_LEV_Pos (2U)
10405#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
10406#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
10407#define FLASH_OPTCR_BFB2_Pos (4U)
10408#define FLASH_OPTCR_BFB2_Msk (0x1UL << FLASH_OPTCR_BFB2_Pos)
10409#define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
10410#define FLASH_OPTCR_WDG_SW_Pos (5U)
10411#define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
10412#define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
10413#define FLASH_OPTCR_nRST_STOP_Pos (6U)
10414#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
10415#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
10416#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
10417#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
10418#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
10419#define FLASH_OPTCR_RDP_Pos (8U)
10420#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
10421#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
10422#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
10423#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
10424#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
10425#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
10426#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
10427#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
10428#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
10429#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
10430#define FLASH_OPTCR_nWRP_Pos (16U)
10431#define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
10432#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
10433#define FLASH_OPTCR_nWRP_0 0x00010000U
10434#define FLASH_OPTCR_nWRP_1 0x00020000U
10435#define FLASH_OPTCR_nWRP_2 0x00040000U
10436#define FLASH_OPTCR_nWRP_3 0x00080000U
10437#define FLASH_OPTCR_nWRP_4 0x00100000U
10438#define FLASH_OPTCR_nWRP_5 0x00200000U
10439#define FLASH_OPTCR_nWRP_6 0x00400000U
10440#define FLASH_OPTCR_nWRP_7 0x00800000U
10441#define FLASH_OPTCR_nWRP_8 0x01000000U
10442#define FLASH_OPTCR_nWRP_9 0x02000000U
10443#define FLASH_OPTCR_nWRP_10 0x04000000U
10444#define FLASH_OPTCR_nWRP_11 0x08000000U
10445#define FLASH_OPTCR_DB1M_Pos (30U)
10446#define FLASH_OPTCR_DB1M_Msk (0x1UL << FLASH_OPTCR_DB1M_Pos)
10447#define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
10448#define FLASH_OPTCR_SPRMOD_Pos (31U)
10449#define FLASH_OPTCR_SPRMOD_Msk (0x1UL << FLASH_OPTCR_SPRMOD_Pos)
10450#define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
10451
10452/****************** Bits definition for FLASH_OPTCR1 register ***************/
10453#define FLASH_OPTCR1_nWRP_Pos (16U)
10454#define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
10455#define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
10456#define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
10457#define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
10458#define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
10459#define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
10460#define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
10461#define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
10462#define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
10463#define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
10464#define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
10465#define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
10466#define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
10467#define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
10468/* Legacy defines */
10469#define FLASH_SR_SOP_Pos FLASH_SR_OPERR_Pos
10470#define FLASH_SR_SOP_Msk FLASH_SR_OPERR_Msk
10471#define FLASH_SR_SOP FLASH_SR_OPERR
10472#define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
10473#define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
10474#define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
10475#define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
10476#define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
10477#define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
10478
10479/******************************************************************************/
10480/* */
10481/* Flexible Memory Controller */
10482/* */
10483/******************************************************************************/
10484/****************** Bit definition for FMC_BCR1 register *******************/
10485#define FMC_BCR1_MBKEN_Pos (0U)
10486#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
10487#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
10488#define FMC_BCR1_MUXEN_Pos (1U)
10489#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
10490#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
10491
10492#define FMC_BCR1_MTYP_Pos (2U)
10493#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
10494#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
10495#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
10496#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
10497
10498#define FMC_BCR1_MWID_Pos (4U)
10499#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
10500#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
10501#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
10502#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
10503
10504#define FMC_BCR1_FACCEN_Pos (6U)
10505#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
10506#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
10507#define FMC_BCR1_BURSTEN_Pos (8U)
10508#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
10509#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
10510#define FMC_BCR1_WAITPOL_Pos (9U)
10511#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
10512#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
10513#define FMC_BCR1_WAITCFG_Pos (11U)
10514#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
10515#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
10516#define FMC_BCR1_WREN_Pos (12U)
10517#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
10518#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
10519#define FMC_BCR1_WAITEN_Pos (13U)
10520#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
10521#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
10522#define FMC_BCR1_EXTMOD_Pos (14U)
10523#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
10524#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
10525#define FMC_BCR1_ASYNCWAIT_Pos (15U)
10526#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
10527#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
10528#define FMC_BCR1_CPSIZE_Pos (16U)
10529#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
10530#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
10531#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
10532#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
10533#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
10534#define FMC_BCR1_CBURSTRW_Pos (19U)
10535#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
10536#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
10537#define FMC_BCR1_CCLKEN_Pos (20U)
10538#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
10539#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
10540#define FMC_BCR1_WFDIS_Pos (21U)
10541#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
10542#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
10543
10544/****************** Bit definition for FMC_BCR2 register *******************/
10545#define FMC_BCR2_MBKEN_Pos (0U)
10546#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
10547#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
10548#define FMC_BCR2_MUXEN_Pos (1U)
10549#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
10550#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
10551
10552#define FMC_BCR2_MTYP_Pos (2U)
10553#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
10554#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
10555#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
10556#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
10557
10558#define FMC_BCR2_MWID_Pos (4U)
10559#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
10560#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
10561#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
10562#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
10563
10564#define FMC_BCR2_FACCEN_Pos (6U)
10565#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
10566#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
10567#define FMC_BCR2_BURSTEN_Pos (8U)
10568#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
10569#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
10570#define FMC_BCR2_WAITPOL_Pos (9U)
10571#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
10572#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
10573#define FMC_BCR2_WAITCFG_Pos (11U)
10574#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
10575#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
10576#define FMC_BCR2_WREN_Pos (12U)
10577#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
10578#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
10579#define FMC_BCR2_WAITEN_Pos (13U)
10580#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
10581#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
10582#define FMC_BCR2_EXTMOD_Pos (14U)
10583#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
10584#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
10585#define FMC_BCR2_ASYNCWAIT_Pos (15U)
10586#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
10587#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
10588#define FMC_BCR2_CBURSTRW_Pos (19U)
10589#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
10590#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
10591
10592/****************** Bit definition for FMC_BCR3 register *******************/
10593#define FMC_BCR3_MBKEN_Pos (0U)
10594#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
10595#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
10596#define FMC_BCR3_MUXEN_Pos (1U)
10597#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
10598#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
10599
10600#define FMC_BCR3_MTYP_Pos (2U)
10601#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
10602#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
10603#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
10604#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
10605
10606#define FMC_BCR3_MWID_Pos (4U)
10607#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
10608#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
10609#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
10610#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
10611
10612#define FMC_BCR3_FACCEN_Pos (6U)
10613#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
10614#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
10615#define FMC_BCR3_BURSTEN_Pos (8U)
10616#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
10617#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
10618#define FMC_BCR3_WAITPOL_Pos (9U)
10619#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
10620#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
10621#define FMC_BCR3_WAITCFG_Pos (11U)
10622#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
10623#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
10624#define FMC_BCR3_WREN_Pos (12U)
10625#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
10626#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
10627#define FMC_BCR3_WAITEN_Pos (13U)
10628#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
10629#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
10630#define FMC_BCR3_EXTMOD_Pos (14U)
10631#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
10632#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
10633#define FMC_BCR3_ASYNCWAIT_Pos (15U)
10634#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
10635#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
10636#define FMC_BCR3_CBURSTRW_Pos (19U)
10637#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
10638#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
10639
10640/****************** Bit definition for FMC_BCR4 register *******************/
10641#define FMC_BCR4_MBKEN_Pos (0U)
10642#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
10643#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
10644#define FMC_BCR4_MUXEN_Pos (1U)
10645#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
10646#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
10647
10648#define FMC_BCR4_MTYP_Pos (2U)
10649#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
10650#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
10651#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
10652#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
10653
10654#define FMC_BCR4_MWID_Pos (4U)
10655#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
10656#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
10657#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
10658#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
10659
10660#define FMC_BCR4_FACCEN_Pos (6U)
10661#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
10662#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
10663#define FMC_BCR4_BURSTEN_Pos (8U)
10664#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
10665#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
10666#define FMC_BCR4_WAITPOL_Pos (9U)
10667#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
10668#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
10669#define FMC_BCR4_WAITCFG_Pos (11U)
10670#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
10671#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
10672#define FMC_BCR4_WREN_Pos (12U)
10673#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
10674#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
10675#define FMC_BCR4_WAITEN_Pos (13U)
10676#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
10677#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
10678#define FMC_BCR4_EXTMOD_Pos (14U)
10679#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
10680#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
10681#define FMC_BCR4_ASYNCWAIT_Pos (15U)
10682#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
10683#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
10684#define FMC_BCR4_CBURSTRW_Pos (19U)
10685#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
10686#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
10687
10688/****************** Bit definition for FMC_BTR1 register ******************/
10689#define FMC_BTR1_ADDSET_Pos (0U)
10690#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
10691#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
10692#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
10693#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
10694#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
10695#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
10696
10697#define FMC_BTR1_ADDHLD_Pos (4U)
10698#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
10699#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
10700#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
10701#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
10702#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
10703#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
10704
10705#define FMC_BTR1_DATAST_Pos (8U)
10706#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
10707#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
10708#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
10709#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
10710#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
10711#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
10712#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
10713#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
10714#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
10715#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
10716
10717#define FMC_BTR1_BUSTURN_Pos (16U)
10718#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
10719#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
10720#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
10721#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
10722#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
10723#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
10724
10725#define FMC_BTR1_CLKDIV_Pos (20U)
10726#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
10727#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
10728#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
10729#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
10730#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
10731#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
10732
10733#define FMC_BTR1_DATLAT_Pos (24U)
10734#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
10735#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
10736#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
10737#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
10738#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
10739#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
10740
10741#define FMC_BTR1_ACCMOD_Pos (28U)
10742#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
10743#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
10744#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
10745#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
10746
10747/****************** Bit definition for FMC_BTR2 register *******************/
10748#define FMC_BTR2_ADDSET_Pos (0U)
10749#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
10750#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
10751#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
10752#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
10753#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
10754#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
10755
10756#define FMC_BTR2_ADDHLD_Pos (4U)
10757#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
10758#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
10759#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
10760#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
10761#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
10762#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
10763
10764#define FMC_BTR2_DATAST_Pos (8U)
10765#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
10766#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
10767#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
10768#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
10769#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
10770#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
10771#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
10772#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
10773#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
10774#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
10775
10776#define FMC_BTR2_BUSTURN_Pos (16U)
10777#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
10778#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
10779#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
10780#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
10781#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
10782#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
10783
10784#define FMC_BTR2_CLKDIV_Pos (20U)
10785#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
10786#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
10787#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
10788#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
10789#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
10790#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
10791
10792#define FMC_BTR2_DATLAT_Pos (24U)
10793#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
10794#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
10795#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
10796#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
10797#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
10798#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
10799
10800#define FMC_BTR2_ACCMOD_Pos (28U)
10801#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
10802#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
10803#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
10804#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
10805
10806/******************* Bit definition for FMC_BTR3 register *******************/
10807#define FMC_BTR3_ADDSET_Pos (0U)
10808#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
10809#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
10810#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
10811#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
10812#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
10813#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
10814
10815#define FMC_BTR3_ADDHLD_Pos (4U)
10816#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
10817#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
10818#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
10819#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
10820#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
10821#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
10822
10823#define FMC_BTR3_DATAST_Pos (8U)
10824#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
10825#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
10826#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
10827#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
10828#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
10829#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
10830#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
10831#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
10832#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
10833#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
10834
10835#define FMC_BTR3_BUSTURN_Pos (16U)
10836#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
10837#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
10838#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
10839#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
10840#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
10841#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
10842
10843#define FMC_BTR3_CLKDIV_Pos (20U)
10844#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
10845#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
10846#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
10847#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
10848#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
10849#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
10850
10851#define FMC_BTR3_DATLAT_Pos (24U)
10852#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
10853#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
10854#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
10855#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
10856#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
10857#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
10858
10859#define FMC_BTR3_ACCMOD_Pos (28U)
10860#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
10861#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
10862#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
10863#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
10864
10865/****************** Bit definition for FMC_BTR4 register *******************/
10866#define FMC_BTR4_ADDSET_Pos (0U)
10867#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
10868#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
10869#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
10870#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
10871#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
10872#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
10873
10874#define FMC_BTR4_ADDHLD_Pos (4U)
10875#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
10876#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
10877#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
10878#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
10879#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
10880#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
10881
10882#define FMC_BTR4_DATAST_Pos (8U)
10883#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
10884#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
10885#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
10886#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
10887#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
10888#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
10889#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
10890#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
10891#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
10892#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
10893
10894#define FMC_BTR4_BUSTURN_Pos (16U)
10895#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
10896#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
10897#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
10898#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
10899#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
10900#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
10901
10902#define FMC_BTR4_CLKDIV_Pos (20U)
10903#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
10904#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
10905#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
10906#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
10907#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
10908#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
10909
10910#define FMC_BTR4_DATLAT_Pos (24U)
10911#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
10912#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
10913#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
10914#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
10915#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
10916#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
10917
10918#define FMC_BTR4_ACCMOD_Pos (28U)
10919#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
10920#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
10921#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
10922#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
10923
10924/****************** Bit definition for FMC_BWTR1 register ******************/
10925#define FMC_BWTR1_ADDSET_Pos (0U)
10926#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
10927#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
10928#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
10929#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
10930#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
10931#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
10932
10933#define FMC_BWTR1_ADDHLD_Pos (4U)
10934#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
10935#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
10936#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
10937#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
10938#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
10939#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
10940
10941#define FMC_BWTR1_DATAST_Pos (8U)
10942#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
10943#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
10944#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
10945#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
10946#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
10947#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
10948#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
10949#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
10950#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
10951#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
10952
10953#define FMC_BWTR1_BUSTURN_Pos (16U)
10954#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
10955#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
10956#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
10957#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
10958#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
10959#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
10960
10961#define FMC_BWTR1_ACCMOD_Pos (28U)
10962#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
10963#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
10964#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
10965#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
10966
10967/****************** Bit definition for FMC_BWTR2 register ******************/
10968#define FMC_BWTR2_ADDSET_Pos (0U)
10969#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
10970#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
10971#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
10972#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
10973#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
10974#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
10975
10976#define FMC_BWTR2_ADDHLD_Pos (4U)
10977#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
10978#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
10979#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
10980#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
10981#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
10982#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
10983
10984#define FMC_BWTR2_DATAST_Pos (8U)
10985#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
10986#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
10987#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
10988#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
10989#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
10990#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
10991#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
10992#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
10993#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
10994#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
10995
10996#define FMC_BWTR2_BUSTURN_Pos (16U)
10997#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
10998#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
10999#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
11000#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
11001#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
11002#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
11003
11004#define FMC_BWTR2_ACCMOD_Pos (28U)
11005#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
11006#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
11007#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
11008#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
11009
11010/****************** Bit definition for FMC_BWTR3 register ******************/
11011#define FMC_BWTR3_ADDSET_Pos (0U)
11012#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
11013#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
11014#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
11015#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
11016#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
11017#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
11018
11019#define FMC_BWTR3_ADDHLD_Pos (4U)
11020#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
11021#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
11022#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
11023#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
11024#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
11025#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
11026
11027#define FMC_BWTR3_DATAST_Pos (8U)
11028#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
11029#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
11030#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
11031#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
11032#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
11033#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
11034#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
11035#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
11036#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
11037#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
11038
11039#define FMC_BWTR3_BUSTURN_Pos (16U)
11040#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
11041#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
11042#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
11043#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
11044#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
11045#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
11046
11047#define FMC_BWTR3_ACCMOD_Pos (28U)
11048#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
11049#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
11050#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
11051#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
11052
11053/****************** Bit definition for FMC_BWTR4 register ******************/
11054#define FMC_BWTR4_ADDSET_Pos (0U)
11055#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
11056#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
11057#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
11058#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
11059#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
11060#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
11061
11062#define FMC_BWTR4_ADDHLD_Pos (4U)
11063#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
11064#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
11065#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
11066#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
11067#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
11068#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
11069
11070#define FMC_BWTR4_DATAST_Pos (8U)
11071#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
11072#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
11073#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
11074#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
11075#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
11076#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
11077#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
11078#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
11079#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
11080#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
11081
11082#define FMC_BWTR4_BUSTURN_Pos (16U)
11083#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
11084#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
11085#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
11086#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
11087#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
11088#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
11089
11090#define FMC_BWTR4_ACCMOD_Pos (28U)
11091#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
11092#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
11093#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
11094#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
11095
11096/****************** Bit definition for FMC_PCR register *******************/
11097#define FMC_PCR_PWAITEN_Pos (1U)
11098#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11099#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11100#define FMC_PCR_PBKEN_Pos (2U)
11101#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11102#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11103#define FMC_PCR_PTYP_Pos (3U)
11104#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
11105#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
11106
11107#define FMC_PCR_PWID_Pos (4U)
11108#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11109#define FMC_PCR_PWID FMC_PCR_PWID_Msk
11110#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11111#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11112
11113#define FMC_PCR_ECCEN_Pos (6U)
11114#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11115#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11116
11117#define FMC_PCR_TCLR_Pos (9U)
11118#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11119#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11120#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11121#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11122#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11123#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11124
11125#define FMC_PCR_TAR_Pos (13U)
11126#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11127#define FMC_PCR_TAR FMC_PCR_TAR_Msk
11128#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11129#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11130#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11131#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11132
11133#define FMC_PCR_ECCPS_Pos (17U)
11134#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11135#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11136#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11137#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11138#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11139
11140/******************* Bit definition for FMC_SR register *******************/
11141#define FMC_SR_IRS_Pos (0U)
11142#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11143#define FMC_SR_IRS FMC_SR_IRS_Msk
11144#define FMC_SR_ILS_Pos (1U)
11145#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11146#define FMC_SR_ILS FMC_SR_ILS_Msk
11147#define FMC_SR_IFS_Pos (2U)
11148#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11149#define FMC_SR_IFS FMC_SR_IFS_Msk
11150#define FMC_SR_IREN_Pos (3U)
11151#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11152#define FMC_SR_IREN FMC_SR_IREN_Msk
11153#define FMC_SR_ILEN_Pos (4U)
11154#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11155#define FMC_SR_ILEN FMC_SR_ILEN_Msk
11156#define FMC_SR_IFEN_Pos (5U)
11157#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11158#define FMC_SR_IFEN FMC_SR_IFEN_Msk
11159#define FMC_SR_FEMPT_Pos (6U)
11160#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11161#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11162
11163/****************** Bit definition for FMC_PMEM register ******************/
11164#define FMC_PMEM_MEMSET2_Pos (0U)
11165#define FMC_PMEM_MEMSET2_Msk (0xFFUL << FMC_PMEM_MEMSET2_Pos)
11166#define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk
11167#define FMC_PMEM_MEMSET2_0 (0x01UL << FMC_PMEM_MEMSET2_Pos)
11168#define FMC_PMEM_MEMSET2_1 (0x02UL << FMC_PMEM_MEMSET2_Pos)
11169#define FMC_PMEM_MEMSET2_2 (0x04UL << FMC_PMEM_MEMSET2_Pos)
11170#define FMC_PMEM_MEMSET2_3 (0x08UL << FMC_PMEM_MEMSET2_Pos)
11171#define FMC_PMEM_MEMSET2_4 (0x10UL << FMC_PMEM_MEMSET2_Pos)
11172#define FMC_PMEM_MEMSET2_5 (0x20UL << FMC_PMEM_MEMSET2_Pos)
11173#define FMC_PMEM_MEMSET2_6 (0x40UL << FMC_PMEM_MEMSET2_Pos)
11174#define FMC_PMEM_MEMSET2_7 (0x80UL << FMC_PMEM_MEMSET2_Pos)
11175
11176#define FMC_PMEM_MEMWAIT2_Pos (8U)
11177#define FMC_PMEM_MEMWAIT2_Msk (0xFFUL << FMC_PMEM_MEMWAIT2_Pos)
11178#define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk
11179#define FMC_PMEM_MEMWAIT2_0 (0x01UL << FMC_PMEM_MEMWAIT2_Pos)
11180#define FMC_PMEM_MEMWAIT2_1 (0x02UL << FMC_PMEM_MEMWAIT2_Pos)
11181#define FMC_PMEM_MEMWAIT2_2 (0x04UL << FMC_PMEM_MEMWAIT2_Pos)
11182#define FMC_PMEM_MEMWAIT2_3 (0x08UL << FMC_PMEM_MEMWAIT2_Pos)
11183#define FMC_PMEM_MEMWAIT2_4 (0x10UL << FMC_PMEM_MEMWAIT2_Pos)
11184#define FMC_PMEM_MEMWAIT2_5 (0x20UL << FMC_PMEM_MEMWAIT2_Pos)
11185#define FMC_PMEM_MEMWAIT2_6 (0x40UL << FMC_PMEM_MEMWAIT2_Pos)
11186#define FMC_PMEM_MEMWAIT2_7 (0x80UL << FMC_PMEM_MEMWAIT2_Pos)
11187
11188#define FMC_PMEM_MEMHOLD2_Pos (16U)
11189#define FMC_PMEM_MEMHOLD2_Msk (0xFFUL << FMC_PMEM_MEMHOLD2_Pos)
11190#define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk
11191#define FMC_PMEM_MEMHOLD2_0 (0x01UL << FMC_PMEM_MEMHOLD2_Pos)
11192#define FMC_PMEM_MEMHOLD2_1 (0x02UL << FMC_PMEM_MEMHOLD2_Pos)
11193#define FMC_PMEM_MEMHOLD2_2 (0x04UL << FMC_PMEM_MEMHOLD2_Pos)
11194#define FMC_PMEM_MEMHOLD2_3 (0x08UL << FMC_PMEM_MEMHOLD2_Pos)
11195#define FMC_PMEM_MEMHOLD2_4 (0x10UL << FMC_PMEM_MEMHOLD2_Pos)
11196#define FMC_PMEM_MEMHOLD2_5 (0x20UL << FMC_PMEM_MEMHOLD2_Pos)
11197#define FMC_PMEM_MEMHOLD2_6 (0x40UL << FMC_PMEM_MEMHOLD2_Pos)
11198#define FMC_PMEM_MEMHOLD2_7 (0x80UL << FMC_PMEM_MEMHOLD2_Pos)
11199
11200#define FMC_PMEM_MEMHIZ2_Pos (24U)
11201#define FMC_PMEM_MEMHIZ2_Msk (0xFFUL << FMC_PMEM_MEMHIZ2_Pos)
11202#define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk
11203#define FMC_PMEM_MEMHIZ2_0 (0x01UL << FMC_PMEM_MEMHIZ2_Pos)
11204#define FMC_PMEM_MEMHIZ2_1 (0x02UL << FMC_PMEM_MEMHIZ2_Pos)
11205#define FMC_PMEM_MEMHIZ2_2 (0x04UL << FMC_PMEM_MEMHIZ2_Pos)
11206#define FMC_PMEM_MEMHIZ2_3 (0x08UL << FMC_PMEM_MEMHIZ2_Pos)
11207#define FMC_PMEM_MEMHIZ2_4 (0x10UL << FMC_PMEM_MEMHIZ2_Pos)
11208#define FMC_PMEM_MEMHIZ2_5 (0x20UL << FMC_PMEM_MEMHIZ2_Pos)
11209#define FMC_PMEM_MEMHIZ2_6 (0x40UL << FMC_PMEM_MEMHIZ2_Pos)
11210#define FMC_PMEM_MEMHIZ2_7 (0x80UL << FMC_PMEM_MEMHIZ2_Pos)
11211
11212/****************** Bit definition for FMC_PATT register ******************/
11213#define FMC_PATT_ATTSET2_Pos (0U)
11214#define FMC_PATT_ATTSET2_Msk (0xFFUL << FMC_PATT_ATTSET2_Pos)
11215#define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk
11216#define FMC_PATT_ATTSET2_0 (0x01UL << FMC_PATT_ATTSET2_Pos)
11217#define FMC_PATT_ATTSET2_1 (0x02UL << FMC_PATT_ATTSET2_Pos)
11218#define FMC_PATT_ATTSET2_2 (0x04UL << FMC_PATT_ATTSET2_Pos)
11219#define FMC_PATT_ATTSET2_3 (0x08UL << FMC_PATT_ATTSET2_Pos)
11220#define FMC_PATT_ATTSET2_4 (0x10UL << FMC_PATT_ATTSET2_Pos)
11221#define FMC_PATT_ATTSET2_5 (0x20UL << FMC_PATT_ATTSET2_Pos)
11222#define FMC_PATT_ATTSET2_6 (0x40UL << FMC_PATT_ATTSET2_Pos)
11223#define FMC_PATT_ATTSET2_7 (0x80UL << FMC_PATT_ATTSET2_Pos)
11224
11225#define FMC_PATT_ATTWAIT2_Pos (8U)
11226#define FMC_PATT_ATTWAIT2_Msk (0xFFUL << FMC_PATT_ATTWAIT2_Pos)
11227#define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk
11228#define FMC_PATT_ATTWAIT2_0 (0x01UL << FMC_PATT_ATTWAIT2_Pos)
11229#define FMC_PATT_ATTWAIT2_1 (0x02UL << FMC_PATT_ATTWAIT2_Pos)
11230#define FMC_PATT_ATTWAIT2_2 (0x04UL << FMC_PATT_ATTWAIT2_Pos)
11231#define FMC_PATT_ATTWAIT2_3 (0x08UL << FMC_PATT_ATTWAIT2_Pos)
11232#define FMC_PATT_ATTWAIT2_4 (0x10UL << FMC_PATT_ATTWAIT2_Pos)
11233#define FMC_PATT_ATTWAIT2_5 (0x20UL << FMC_PATT_ATTWAIT2_Pos)
11234#define FMC_PATT_ATTWAIT2_6 (0x40UL << FMC_PATT_ATTWAIT2_Pos)
11235#define FMC_PATT_ATTWAIT2_7 (0x80UL << FMC_PATT_ATTWAIT2_Pos)
11236
11237#define FMC_PATT_ATTHOLD2_Pos (16U)
11238#define FMC_PATT_ATTHOLD2_Msk (0xFFUL << FMC_PATT_ATTHOLD2_Pos)
11239#define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk
11240#define FMC_PATT_ATTHOLD2_0 (0x01UL << FMC_PATT_ATTHOLD2_Pos)
11241#define FMC_PATT_ATTHOLD2_1 (0x02UL << FMC_PATT_ATTHOLD2_Pos)
11242#define FMC_PATT_ATTHOLD2_2 (0x04UL << FMC_PATT_ATTHOLD2_Pos)
11243#define FMC_PATT_ATTHOLD2_3 (0x08UL << FMC_PATT_ATTHOLD2_Pos)
11244#define FMC_PATT_ATTHOLD2_4 (0x10UL << FMC_PATT_ATTHOLD2_Pos)
11245#define FMC_PATT_ATTHOLD2_5 (0x20UL << FMC_PATT_ATTHOLD2_Pos)
11246#define FMC_PATT_ATTHOLD2_6 (0x40UL << FMC_PATT_ATTHOLD2_Pos)
11247#define FMC_PATT_ATTHOLD2_7 (0x80UL << FMC_PATT_ATTHOLD2_Pos)
11248
11249#define FMC_PATT_ATTHIZ2_Pos (24U)
11250#define FMC_PATT_ATTHIZ2_Msk (0xFFUL << FMC_PATT_ATTHIZ2_Pos)
11251#define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk
11252#define FMC_PATT_ATTHIZ2_0 (0x01UL << FMC_PATT_ATTHIZ2_Pos)
11253#define FMC_PATT_ATTHIZ2_1 (0x02UL << FMC_PATT_ATTHIZ2_Pos)
11254#define FMC_PATT_ATTHIZ2_2 (0x04UL << FMC_PATT_ATTHIZ2_Pos)
11255#define FMC_PATT_ATTHIZ2_3 (0x08UL << FMC_PATT_ATTHIZ2_Pos)
11256#define FMC_PATT_ATTHIZ2_4 (0x10UL << FMC_PATT_ATTHIZ2_Pos)
11257#define FMC_PATT_ATTHIZ2_5 (0x20UL << FMC_PATT_ATTHIZ2_Pos)
11258#define FMC_PATT_ATTHIZ2_6 (0x40UL << FMC_PATT_ATTHIZ2_Pos)
11259#define FMC_PATT_ATTHIZ2_7 (0x80UL << FMC_PATT_ATTHIZ2_Pos)
11260
11261/****************** Bit definition for FMC_ECCR register ******************/
11262#define FMC_ECCR_ECC2_Pos (0U)
11263#define FMC_ECCR_ECC2_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC2_Pos)
11264#define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk
11265
11266/****************** Bit definition for FMC_SDCR1 register ******************/
11267#define FMC_SDCR1_NC_Pos (0U)
11268#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
11269#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
11270#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
11271#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
11272
11273#define FMC_SDCR1_NR_Pos (2U)
11274#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
11275#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
11276#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
11277#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
11278
11279#define FMC_SDCR1_MWID_Pos (4U)
11280#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
11281#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
11282#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
11283#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
11284
11285#define FMC_SDCR1_NB_Pos (6U)
11286#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
11287#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
11288
11289#define FMC_SDCR1_CAS_Pos (7U)
11290#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
11291#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
11292#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
11293#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
11294
11295#define FMC_SDCR1_WP_Pos (9U)
11296#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
11297#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
11298
11299#define FMC_SDCR1_SDCLK_Pos (10U)
11300#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
11301#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
11302#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
11303#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
11304
11305#define FMC_SDCR1_RBURST_Pos (12U)
11306#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
11307#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
11308
11309#define FMC_SDCR1_RPIPE_Pos (13U)
11310#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
11311#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
11312#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
11313#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
11314
11315/****************** Bit definition for FMC_SDCR2 register ******************/
11316#define FMC_SDCR2_NC_Pos (0U)
11317#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
11318#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
11319#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
11320#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
11321
11322#define FMC_SDCR2_NR_Pos (2U)
11323#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
11324#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
11325#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
11326#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
11327
11328#define FMC_SDCR2_MWID_Pos (4U)
11329#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
11330#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
11331#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
11332#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
11333
11334#define FMC_SDCR2_NB_Pos (6U)
11335#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
11336#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
11337
11338#define FMC_SDCR2_CAS_Pos (7U)
11339#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
11340#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
11341#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
11342#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
11343
11344#define FMC_SDCR2_WP_Pos (9U)
11345#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
11346#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
11347
11348#define FMC_SDCR2_SDCLK_Pos (10U)
11349#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
11350#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
11351#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
11352#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
11353
11354#define FMC_SDCR2_RBURST_Pos (12U)
11355#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
11356#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
11357
11358#define FMC_SDCR2_RPIPE_Pos (13U)
11359#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
11360#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
11361#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
11362#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
11363
11364/****************** Bit definition for FMC_SDTR1 register ******************/
11365#define FMC_SDTR1_TMRD_Pos (0U)
11366#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
11367#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
11368#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
11369#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
11370#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
11371#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
11372
11373#define FMC_SDTR1_TXSR_Pos (4U)
11374#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
11375#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
11376#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
11377#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
11378#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
11379#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
11380
11381#define FMC_SDTR1_TRAS_Pos (8U)
11382#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
11383#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
11384#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
11385#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
11386#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
11387#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
11388
11389#define FMC_SDTR1_TRC_Pos (12U)
11390#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
11391#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
11392#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
11393#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
11394#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
11395
11396#define FMC_SDTR1_TWR_Pos (16U)
11397#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
11398#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
11399#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
11400#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
11401#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
11402
11403#define FMC_SDTR1_TRP_Pos (20U)
11404#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
11405#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
11406#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
11407#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
11408#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
11409
11410#define FMC_SDTR1_TRCD_Pos (24U)
11411#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
11412#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
11413#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
11414#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
11415#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
11416
11417/****************** Bit definition for FMC_SDTR2 register ******************/
11418#define FMC_SDTR2_TMRD_Pos (0U)
11419#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
11420#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
11421#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
11422#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
11423#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
11424#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
11425
11426#define FMC_SDTR2_TXSR_Pos (4U)
11427#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
11428#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
11429#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
11430#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
11431#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
11432#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
11433
11434#define FMC_SDTR2_TRAS_Pos (8U)
11435#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
11436#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
11437#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
11438#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
11439#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
11440#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
11441
11442#define FMC_SDTR2_TRC_Pos (12U)
11443#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
11444#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
11445#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
11446#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
11447#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
11448
11449#define FMC_SDTR2_TWR_Pos (16U)
11450#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
11451#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
11452#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
11453#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
11454#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
11455
11456#define FMC_SDTR2_TRP_Pos (20U)
11457#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
11458#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
11459#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
11460#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
11461#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
11462
11463#define FMC_SDTR2_TRCD_Pos (24U)
11464#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
11465#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
11466#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
11467#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
11468#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
11469
11470/****************** Bit definition for FMC_SDCMR register ******************/
11471#define FMC_SDCMR_MODE_Pos (0U)
11472#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11473#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11474#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11475#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11476#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
11477
11478#define FMC_SDCMR_CTB2_Pos (3U)
11479#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11480#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11481
11482#define FMC_SDCMR_CTB1_Pos (4U)
11483#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11484#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11485
11486#define FMC_SDCMR_NRFS_Pos (5U)
11487#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11488#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11489#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11490#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11491#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11492#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11493
11494#define FMC_SDCMR_MRD_Pos (9U)
11495#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11496#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11497
11498/****************** Bit definition for FMC_SDRTR register ******************/
11499#define FMC_SDRTR_CRE_Pos (0U)
11500#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
11501#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
11502
11503#define FMC_SDRTR_COUNT_Pos (1U)
11504#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
11505#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
11506
11507#define FMC_SDRTR_REIE_Pos (14U)
11508#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
11509#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
11510
11511/****************** Bit definition for FMC_SDSR register ******************/
11512#define FMC_SDSR_RE_Pos (0U)
11513#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
11514#define FMC_SDSR_RE FMC_SDSR_RE_Msk
11515
11516#define FMC_SDSR_MODES1_Pos (1U)
11517#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
11518#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
11519#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
11520#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
11521
11522#define FMC_SDSR_MODES2_Pos (3U)
11523#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
11524#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
11525#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
11526#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
11527#define FMC_SDSR_BUSY_Pos (5U)
11528#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
11529#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
11530
11531/******************************************************************************/
11532/* */
11533/* General Purpose I/O */
11534/* */
11535/******************************************************************************/
11536/****************** Bits definition for GPIO_MODER register *****************/
11537#define GPIO_MODER_MODER0_Pos (0U)
11538#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
11539#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
11540#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
11541#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
11542#define GPIO_MODER_MODER1_Pos (2U)
11543#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
11544#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
11545#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
11546#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
11547#define GPIO_MODER_MODER2_Pos (4U)
11548#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
11549#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
11550#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
11551#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
11552#define GPIO_MODER_MODER3_Pos (6U)
11553#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
11554#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
11555#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
11556#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
11557#define GPIO_MODER_MODER4_Pos (8U)
11558#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
11559#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
11560#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
11561#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
11562#define GPIO_MODER_MODER5_Pos (10U)
11563#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
11564#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
11565#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
11566#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
11567#define GPIO_MODER_MODER6_Pos (12U)
11568#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
11569#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
11570#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
11571#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
11572#define GPIO_MODER_MODER7_Pos (14U)
11573#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
11574#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
11575#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
11576#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
11577#define GPIO_MODER_MODER8_Pos (16U)
11578#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
11579#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
11580#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
11581#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
11582#define GPIO_MODER_MODER9_Pos (18U)
11583#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
11584#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
11585#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
11586#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
11587#define GPIO_MODER_MODER10_Pos (20U)
11588#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
11589#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
11590#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
11591#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
11592#define GPIO_MODER_MODER11_Pos (22U)
11593#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
11594#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
11595#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
11596#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
11597#define GPIO_MODER_MODER12_Pos (24U)
11598#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
11599#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
11600#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
11601#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
11602#define GPIO_MODER_MODER13_Pos (26U)
11603#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
11604#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
11605#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
11606#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
11607#define GPIO_MODER_MODER14_Pos (28U)
11608#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
11609#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
11610#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
11611#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
11612#define GPIO_MODER_MODER15_Pos (30U)
11613#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
11614#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
11615#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
11616#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
11617
11618/* Legacy defines */
11619#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
11620#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
11621#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
11622#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
11623#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
11624#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
11625#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
11626#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
11627#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
11628#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
11629#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
11630#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
11631#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
11632#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
11633#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
11634#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
11635#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
11636#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
11637#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
11638#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
11639#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
11640#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
11641#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
11642#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
11643#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
11644#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
11645#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
11646#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
11647#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
11648#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
11649#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
11650#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
11651#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
11652#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
11653#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
11654#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
11655#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
11656#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
11657#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
11658#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
11659#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
11660#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
11661#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
11662#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
11663#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
11664#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
11665#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
11666#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
11667#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
11668#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
11669#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
11670#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
11671#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
11672#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
11673#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
11674#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
11675#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
11676#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
11677#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
11678#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
11679#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
11680#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
11681#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
11682#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
11683#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
11684#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
11685#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
11686#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
11687#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
11688#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
11689#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
11690#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
11691#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
11692#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
11693#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
11694#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
11695#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
11696#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
11697#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
11698#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
11699
11700/****************** Bits definition for GPIO_OTYPER register ****************/
11701#define GPIO_OTYPER_OT0_Pos (0U)
11702#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
11703#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11704#define GPIO_OTYPER_OT1_Pos (1U)
11705#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
11706#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11707#define GPIO_OTYPER_OT2_Pos (2U)
11708#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
11709#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11710#define GPIO_OTYPER_OT3_Pos (3U)
11711#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
11712#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11713#define GPIO_OTYPER_OT4_Pos (4U)
11714#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
11715#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11716#define GPIO_OTYPER_OT5_Pos (5U)
11717#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
11718#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11719#define GPIO_OTYPER_OT6_Pos (6U)
11720#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
11721#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11722#define GPIO_OTYPER_OT7_Pos (7U)
11723#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
11724#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11725#define GPIO_OTYPER_OT8_Pos (8U)
11726#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
11727#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11728#define GPIO_OTYPER_OT9_Pos (9U)
11729#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
11730#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11731#define GPIO_OTYPER_OT10_Pos (10U)
11732#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
11733#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11734#define GPIO_OTYPER_OT11_Pos (11U)
11735#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
11736#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11737#define GPIO_OTYPER_OT12_Pos (12U)
11738#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
11739#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11740#define GPIO_OTYPER_OT13_Pos (13U)
11741#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
11742#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11743#define GPIO_OTYPER_OT14_Pos (14U)
11744#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
11745#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11746#define GPIO_OTYPER_OT15_Pos (15U)
11747#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
11748#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11749
11750/* Legacy defines */
11751#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
11752#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
11753#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
11754#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
11755#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
11756#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
11757#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
11758#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
11759#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
11760#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
11761#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
11762#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
11763#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
11764#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
11765#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
11766#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
11767
11768/****************** Bits definition for GPIO_OSPEEDR register ***************/
11769#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11770#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
11771#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11772#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
11773#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
11774#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11775#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
11776#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11777#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
11778#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
11779#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11780#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
11781#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11782#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
11783#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
11784#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11785#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
11786#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11787#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
11788#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
11789#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11790#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
11791#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11792#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
11793#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
11794#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11795#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
11796#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11797#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
11798#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
11799#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11800#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
11801#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11802#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
11803#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
11804#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11805#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
11806#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11807#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
11808#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
11809#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11810#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
11811#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11812#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
11813#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
11814#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11815#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
11816#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11817#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
11818#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
11819#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11820#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
11821#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11822#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
11823#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
11824#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11825#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
11826#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11827#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
11828#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
11829#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11830#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
11831#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11832#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
11833#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
11834#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11835#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
11836#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11837#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
11838#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
11839#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11840#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
11841#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11842#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
11843#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
11844#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11845#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
11846#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11847#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
11848#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
11849
11850/* Legacy defines */
11851#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
11852#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
11853#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
11854#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
11855#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
11856#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
11857#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
11858#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
11859#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
11860#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
11861#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
11862#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
11863#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
11864#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
11865#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
11866#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
11867#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
11868#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
11869#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
11870#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
11871#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
11872#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
11873#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
11874#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
11875#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
11876#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
11877#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
11878#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
11879#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
11880#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
11881#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
11882#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
11883#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
11884#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
11885#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
11886#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
11887#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
11888#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
11889#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
11890#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
11891#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
11892#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
11893#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
11894#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
11895#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
11896#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
11897#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
11898#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
11899
11900/****************** Bits definition for GPIO_PUPDR register *****************/
11901#define GPIO_PUPDR_PUPD0_Pos (0U)
11902#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
11903#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11904#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
11905#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
11906#define GPIO_PUPDR_PUPD1_Pos (2U)
11907#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
11908#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11909#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
11910#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
11911#define GPIO_PUPDR_PUPD2_Pos (4U)
11912#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
11913#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11914#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
11915#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
11916#define GPIO_PUPDR_PUPD3_Pos (6U)
11917#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
11918#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11919#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
11920#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
11921#define GPIO_PUPDR_PUPD4_Pos (8U)
11922#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
11923#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11924#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
11925#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
11926#define GPIO_PUPDR_PUPD5_Pos (10U)
11927#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
11928#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11929#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
11930#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
11931#define GPIO_PUPDR_PUPD6_Pos (12U)
11932#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
11933#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11934#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
11935#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
11936#define GPIO_PUPDR_PUPD7_Pos (14U)
11937#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
11938#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11939#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
11940#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
11941#define GPIO_PUPDR_PUPD8_Pos (16U)
11942#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
11943#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11944#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
11945#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
11946#define GPIO_PUPDR_PUPD9_Pos (18U)
11947#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
11948#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11949#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
11950#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
11951#define GPIO_PUPDR_PUPD10_Pos (20U)
11952#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
11953#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11954#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
11955#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
11956#define GPIO_PUPDR_PUPD11_Pos (22U)
11957#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
11958#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11959#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
11960#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
11961#define GPIO_PUPDR_PUPD12_Pos (24U)
11962#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
11963#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11964#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
11965#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
11966#define GPIO_PUPDR_PUPD13_Pos (26U)
11967#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
11968#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11969#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
11970#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
11971#define GPIO_PUPDR_PUPD14_Pos (28U)
11972#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
11973#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11974#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
11975#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
11976#define GPIO_PUPDR_PUPD15_Pos (30U)
11977#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
11978#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11979#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
11980#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
11981
11982/* Legacy defines */
11983#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
11984#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
11985#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
11986#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
11987#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
11988#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
11989#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
11990#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
11991#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
11992#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
11993#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
11994#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
11995#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
11996#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
11997#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
11998#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
11999#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
12000#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
12001#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
12002#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
12003#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
12004#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
12005#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
12006#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
12007#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
12008#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
12009#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
12010#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
12011#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
12012#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
12013#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
12014#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
12015#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
12016#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
12017#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
12018#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
12019#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
12020#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
12021#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
12022#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
12023#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
12024#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
12025#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
12026#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
12027#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
12028#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
12029#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
12030#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
12031
12032/****************** Bits definition for GPIO_IDR register *******************/
12033#define GPIO_IDR_ID0_Pos (0U)
12034#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
12035#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12036#define GPIO_IDR_ID1_Pos (1U)
12037#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
12038#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12039#define GPIO_IDR_ID2_Pos (2U)
12040#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
12041#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12042#define GPIO_IDR_ID3_Pos (3U)
12043#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
12044#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12045#define GPIO_IDR_ID4_Pos (4U)
12046#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
12047#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12048#define GPIO_IDR_ID5_Pos (5U)
12049#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
12050#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12051#define GPIO_IDR_ID6_Pos (6U)
12052#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
12053#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12054#define GPIO_IDR_ID7_Pos (7U)
12055#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
12056#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12057#define GPIO_IDR_ID8_Pos (8U)
12058#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
12059#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12060#define GPIO_IDR_ID9_Pos (9U)
12061#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
12062#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12063#define GPIO_IDR_ID10_Pos (10U)
12064#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
12065#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12066#define GPIO_IDR_ID11_Pos (11U)
12067#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
12068#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12069#define GPIO_IDR_ID12_Pos (12U)
12070#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
12071#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12072#define GPIO_IDR_ID13_Pos (13U)
12073#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
12074#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12075#define GPIO_IDR_ID14_Pos (14U)
12076#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
12077#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12078#define GPIO_IDR_ID15_Pos (15U)
12079#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
12080#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12081
12082/* Legacy defines */
12083#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
12084#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
12085#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
12086#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
12087#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
12088#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
12089#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
12090#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
12091#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
12092#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
12093#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
12094#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
12095#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
12096#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
12097#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
12098#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
12099
12100/****************** Bits definition for GPIO_ODR register *******************/
12101#define GPIO_ODR_OD0_Pos (0U)
12102#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
12103#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12104#define GPIO_ODR_OD1_Pos (1U)
12105#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
12106#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12107#define GPIO_ODR_OD2_Pos (2U)
12108#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
12109#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12110#define GPIO_ODR_OD3_Pos (3U)
12111#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
12112#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12113#define GPIO_ODR_OD4_Pos (4U)
12114#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
12115#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12116#define GPIO_ODR_OD5_Pos (5U)
12117#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
12118#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12119#define GPIO_ODR_OD6_Pos (6U)
12120#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
12121#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12122#define GPIO_ODR_OD7_Pos (7U)
12123#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
12124#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12125#define GPIO_ODR_OD8_Pos (8U)
12126#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
12127#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12128#define GPIO_ODR_OD9_Pos (9U)
12129#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
12130#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12131#define GPIO_ODR_OD10_Pos (10U)
12132#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
12133#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12134#define GPIO_ODR_OD11_Pos (11U)
12135#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
12136#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12137#define GPIO_ODR_OD12_Pos (12U)
12138#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
12139#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12140#define GPIO_ODR_OD13_Pos (13U)
12141#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
12142#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12143#define GPIO_ODR_OD14_Pos (14U)
12144#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
12145#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12146#define GPIO_ODR_OD15_Pos (15U)
12147#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
12148#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12149/* Legacy defines */
12150#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
12151#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
12152#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
12153#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
12154#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
12155#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
12156#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
12157#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
12158#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
12159#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
12160#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
12161#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
12162#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
12163#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
12164#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
12165#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
12166
12167/****************** Bits definition for GPIO_BSRR register ******************/
12168#define GPIO_BSRR_BS0_Pos (0U)
12169#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
12170#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12171#define GPIO_BSRR_BS1_Pos (1U)
12172#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
12173#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12174#define GPIO_BSRR_BS2_Pos (2U)
12175#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
12176#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12177#define GPIO_BSRR_BS3_Pos (3U)
12178#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
12179#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12180#define GPIO_BSRR_BS4_Pos (4U)
12181#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
12182#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12183#define GPIO_BSRR_BS5_Pos (5U)
12184#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
12185#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12186#define GPIO_BSRR_BS6_Pos (6U)
12187#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
12188#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12189#define GPIO_BSRR_BS7_Pos (7U)
12190#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
12191#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12192#define GPIO_BSRR_BS8_Pos (8U)
12193#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
12194#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12195#define GPIO_BSRR_BS9_Pos (9U)
12196#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
12197#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12198#define GPIO_BSRR_BS10_Pos (10U)
12199#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
12200#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12201#define GPIO_BSRR_BS11_Pos (11U)
12202#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
12203#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12204#define GPIO_BSRR_BS12_Pos (12U)
12205#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
12206#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12207#define GPIO_BSRR_BS13_Pos (13U)
12208#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
12209#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12210#define GPIO_BSRR_BS14_Pos (14U)
12211#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
12212#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12213#define GPIO_BSRR_BS15_Pos (15U)
12214#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
12215#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12216#define GPIO_BSRR_BR0_Pos (16U)
12217#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
12218#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12219#define GPIO_BSRR_BR1_Pos (17U)
12220#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
12221#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12222#define GPIO_BSRR_BR2_Pos (18U)
12223#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
12224#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12225#define GPIO_BSRR_BR3_Pos (19U)
12226#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
12227#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12228#define GPIO_BSRR_BR4_Pos (20U)
12229#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
12230#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12231#define GPIO_BSRR_BR5_Pos (21U)
12232#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
12233#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12234#define GPIO_BSRR_BR6_Pos (22U)
12235#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
12236#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12237#define GPIO_BSRR_BR7_Pos (23U)
12238#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
12239#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12240#define GPIO_BSRR_BR8_Pos (24U)
12241#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
12242#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12243#define GPIO_BSRR_BR9_Pos (25U)
12244#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
12245#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12246#define GPIO_BSRR_BR10_Pos (26U)
12247#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
12248#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12249#define GPIO_BSRR_BR11_Pos (27U)
12250#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
12251#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12252#define GPIO_BSRR_BR12_Pos (28U)
12253#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
12254#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12255#define GPIO_BSRR_BR13_Pos (29U)
12256#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
12257#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12258#define GPIO_BSRR_BR14_Pos (30U)
12259#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
12260#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12261#define GPIO_BSRR_BR15_Pos (31U)
12262#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
12263#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12264
12265/* Legacy defines */
12266#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
12267#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
12268#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
12269#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
12270#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
12271#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
12272#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
12273#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
12274#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
12275#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
12276#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
12277#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
12278#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
12279#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
12280#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
12281#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
12282#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
12283#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
12284#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
12285#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
12286#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
12287#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
12288#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
12289#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
12290#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
12291#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
12292#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
12293#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
12294#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
12295#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
12296#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
12297#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
12298#define GPIO_BRR_BR0 GPIO_BSRR_BR0
12299#define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
12300#define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
12301#define GPIO_BRR_BR1 GPIO_BSRR_BR1
12302#define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
12303#define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
12304#define GPIO_BRR_BR2 GPIO_BSRR_BR2
12305#define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
12306#define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
12307#define GPIO_BRR_BR3 GPIO_BSRR_BR3
12308#define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
12309#define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
12310#define GPIO_BRR_BR4 GPIO_BSRR_BR4
12311#define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
12312#define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
12313#define GPIO_BRR_BR5 GPIO_BSRR_BR5
12314#define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
12315#define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
12316#define GPIO_BRR_BR6 GPIO_BSRR_BR6
12317#define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
12318#define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
12319#define GPIO_BRR_BR7 GPIO_BSRR_BR7
12320#define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
12321#define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
12322#define GPIO_BRR_BR8 GPIO_BSRR_BR8
12323#define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
12324#define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
12325#define GPIO_BRR_BR9 GPIO_BSRR_BR9
12326#define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
12327#define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
12328#define GPIO_BRR_BR10 GPIO_BSRR_BR10
12329#define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
12330#define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
12331#define GPIO_BRR_BR11 GPIO_BSRR_BR11
12332#define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
12333#define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
12334#define GPIO_BRR_BR12 GPIO_BSRR_BR12
12335#define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
12336#define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
12337#define GPIO_BRR_BR13 GPIO_BSRR_BR13
12338#define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
12339#define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
12340#define GPIO_BRR_BR14 GPIO_BSRR_BR14
12341#define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
12342#define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
12343#define GPIO_BRR_BR15 GPIO_BSRR_BR15
12344#define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
12345#define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
12346/****************** Bit definition for GPIO_LCKR register *********************/
12347#define GPIO_LCKR_LCK0_Pos (0U)
12348#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
12349#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12350#define GPIO_LCKR_LCK1_Pos (1U)
12351#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
12352#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12353#define GPIO_LCKR_LCK2_Pos (2U)
12354#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
12355#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12356#define GPIO_LCKR_LCK3_Pos (3U)
12357#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
12358#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12359#define GPIO_LCKR_LCK4_Pos (4U)
12360#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
12361#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12362#define GPIO_LCKR_LCK5_Pos (5U)
12363#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
12364#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12365#define GPIO_LCKR_LCK6_Pos (6U)
12366#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
12367#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12368#define GPIO_LCKR_LCK7_Pos (7U)
12369#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
12370#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12371#define GPIO_LCKR_LCK8_Pos (8U)
12372#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
12373#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12374#define GPIO_LCKR_LCK9_Pos (9U)
12375#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
12376#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12377#define GPIO_LCKR_LCK10_Pos (10U)
12378#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12379#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12380#define GPIO_LCKR_LCK11_Pos (11U)
12381#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12382#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12383#define GPIO_LCKR_LCK12_Pos (12U)
12384#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12385#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12386#define GPIO_LCKR_LCK13_Pos (13U)
12387#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12388#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12389#define GPIO_LCKR_LCK14_Pos (14U)
12390#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12391#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12392#define GPIO_LCKR_LCK15_Pos (15U)
12393#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12394#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12395#define GPIO_LCKR_LCKK_Pos (16U)
12396#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12397#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12398/****************** Bit definition for GPIO_AFRL register *********************/
12399#define GPIO_AFRL_AFSEL0_Pos (0U)
12400#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12401#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12402#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12403#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12404#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12405#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12406#define GPIO_AFRL_AFSEL1_Pos (4U)
12407#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12408#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12409#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12410#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12411#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12412#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12413#define GPIO_AFRL_AFSEL2_Pos (8U)
12414#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12415#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12416#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12417#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12418#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12419#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12420#define GPIO_AFRL_AFSEL3_Pos (12U)
12421#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12422#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12423#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12424#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12425#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12426#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12427#define GPIO_AFRL_AFSEL4_Pos (16U)
12428#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12429#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12430#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12431#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12432#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12433#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12434#define GPIO_AFRL_AFSEL5_Pos (20U)
12435#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12436#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12437#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12438#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12439#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12440#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12441#define GPIO_AFRL_AFSEL6_Pos (24U)
12442#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12443#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12444#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12445#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12446#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12447#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12448#define GPIO_AFRL_AFSEL7_Pos (28U)
12449#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12450#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12451#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12452#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12453#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12454#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12455
12456/* Legacy defines */
12457#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12458#define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
12459#define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
12460#define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
12461#define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
12462#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12463#define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
12464#define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
12465#define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
12466#define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
12467#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12468#define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
12469#define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
12470#define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
12471#define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
12472#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12473#define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
12474#define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
12475#define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
12476#define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
12477#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12478#define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
12479#define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
12480#define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
12481#define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
12482#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12483#define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
12484#define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
12485#define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
12486#define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
12487#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12488#define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
12489#define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
12490#define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
12491#define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
12492#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12493#define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
12494#define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
12495#define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
12496#define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
12497
12498/****************** Bit definition for GPIO_AFRH register *********************/
12499#define GPIO_AFRH_AFSEL8_Pos (0U)
12500#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12501#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12502#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12503#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12504#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12505#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12506#define GPIO_AFRH_AFSEL9_Pos (4U)
12507#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12508#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12509#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12510#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12511#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12512#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12513#define GPIO_AFRH_AFSEL10_Pos (8U)
12514#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12515#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12516#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12517#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12518#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12519#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12520#define GPIO_AFRH_AFSEL11_Pos (12U)
12521#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12522#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12523#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12524#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12525#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12526#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12527#define GPIO_AFRH_AFSEL12_Pos (16U)
12528#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12529#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12530#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12531#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12532#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12533#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12534#define GPIO_AFRH_AFSEL13_Pos (20U)
12535#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12536#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12537#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12538#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12539#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12540#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12541#define GPIO_AFRH_AFSEL14_Pos (24U)
12542#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12543#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12544#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12545#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12546#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12547#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12548#define GPIO_AFRH_AFSEL15_Pos (28U)
12549#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12550#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12551#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12552#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12553#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12554#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12555
12556/* Legacy defines */
12557#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12558#define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
12559#define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
12560#define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
12561#define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
12562#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12563#define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
12564#define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
12565#define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
12566#define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
12567#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12568#define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
12569#define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
12570#define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
12571#define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
12572#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12573#define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
12574#define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
12575#define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
12576#define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
12577#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12578#define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
12579#define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
12580#define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
12581#define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
12582#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12583#define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
12584#define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
12585#define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
12586#define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
12587#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12588#define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
12589#define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
12590#define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
12591#define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
12592#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12593#define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
12594#define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
12595#define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
12596#define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
12597
12598
12599/******************************************************************************/
12600/* */
12601/* Inter-integrated Circuit Interface */
12602/* */
12603/******************************************************************************/
12604/******************* Bit definition for I2C_CR1 register ********************/
12605#define I2C_CR1_PE_Pos (0U)
12606#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
12607#define I2C_CR1_PE I2C_CR1_PE_Msk
12608#define I2C_CR1_SMBUS_Pos (1U)
12609#define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
12610#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
12611#define I2C_CR1_SMBTYPE_Pos (3U)
12612#define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
12613#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
12614#define I2C_CR1_ENARP_Pos (4U)
12615#define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
12616#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
12617#define I2C_CR1_ENPEC_Pos (5U)
12618#define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
12619#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
12620#define I2C_CR1_ENGC_Pos (6U)
12621#define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
12622#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
12623#define I2C_CR1_NOSTRETCH_Pos (7U)
12624#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
12625#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
12626#define I2C_CR1_START_Pos (8U)
12627#define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
12628#define I2C_CR1_START I2C_CR1_START_Msk
12629#define I2C_CR1_STOP_Pos (9U)
12630#define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
12631#define I2C_CR1_STOP I2C_CR1_STOP_Msk
12632#define I2C_CR1_ACK_Pos (10U)
12633#define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
12634#define I2C_CR1_ACK I2C_CR1_ACK_Msk
12635#define I2C_CR1_POS_Pos (11U)
12636#define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
12637#define I2C_CR1_POS I2C_CR1_POS_Msk
12638#define I2C_CR1_PEC_Pos (12U)
12639#define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
12640#define I2C_CR1_PEC I2C_CR1_PEC_Msk
12641#define I2C_CR1_ALERT_Pos (13U)
12642#define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
12643#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
12644#define I2C_CR1_SWRST_Pos (15U)
12645#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
12646#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
12647
12648/******************* Bit definition for I2C_CR2 register ********************/
12649#define I2C_CR2_FREQ_Pos (0U)
12650#define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
12651#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
12652#define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
12653#define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
12654#define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
12655#define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
12656#define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
12657#define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
12658
12659#define I2C_CR2_ITERREN_Pos (8U)
12660#define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
12661#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
12662#define I2C_CR2_ITEVTEN_Pos (9U)
12663#define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
12664#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
12665#define I2C_CR2_ITBUFEN_Pos (10U)
12666#define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
12667#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
12668#define I2C_CR2_DMAEN_Pos (11U)
12669#define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
12670#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
12671#define I2C_CR2_LAST_Pos (12U)
12672#define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
12673#define I2C_CR2_LAST I2C_CR2_LAST_Msk
12674
12675/******************* Bit definition for I2C_OAR1 register *******************/
12676#define I2C_OAR1_ADD1_7 0x000000FEU
12677#define I2C_OAR1_ADD8_9 0x00000300U
12678
12679#define I2C_OAR1_ADD0_Pos (0U)
12680#define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
12681#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
12682#define I2C_OAR1_ADD1_Pos (1U)
12683#define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
12684#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
12685#define I2C_OAR1_ADD2_Pos (2U)
12686#define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
12687#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
12688#define I2C_OAR1_ADD3_Pos (3U)
12689#define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
12690#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
12691#define I2C_OAR1_ADD4_Pos (4U)
12692#define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
12693#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
12694#define I2C_OAR1_ADD5_Pos (5U)
12695#define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
12696#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
12697#define I2C_OAR1_ADD6_Pos (6U)
12698#define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
12699#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
12700#define I2C_OAR1_ADD7_Pos (7U)
12701#define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
12702#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
12703#define I2C_OAR1_ADD8_Pos (8U)
12704#define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
12705#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
12706#define I2C_OAR1_ADD9_Pos (9U)
12707#define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
12708#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
12709
12710#define I2C_OAR1_ADDMODE_Pos (15U)
12711#define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
12712#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
12713
12714/******************* Bit definition for I2C_OAR2 register *******************/
12715#define I2C_OAR2_ENDUAL_Pos (0U)
12716#define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
12717#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
12718#define I2C_OAR2_ADD2_Pos (1U)
12719#define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
12720#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
12721
12722/******************** Bit definition for I2C_DR register ********************/
12723#define I2C_DR_DR_Pos (0U)
12724#define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
12725#define I2C_DR_DR I2C_DR_DR_Msk
12726
12727/******************* Bit definition for I2C_SR1 register ********************/
12728#define I2C_SR1_SB_Pos (0U)
12729#define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
12730#define I2C_SR1_SB I2C_SR1_SB_Msk
12731#define I2C_SR1_ADDR_Pos (1U)
12732#define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
12733#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
12734#define I2C_SR1_BTF_Pos (2U)
12735#define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
12736#define I2C_SR1_BTF I2C_SR1_BTF_Msk
12737#define I2C_SR1_ADD10_Pos (3U)
12738#define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
12739#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
12740#define I2C_SR1_STOPF_Pos (4U)
12741#define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
12742#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
12743#define I2C_SR1_RXNE_Pos (6U)
12744#define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
12745#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
12746#define I2C_SR1_TXE_Pos (7U)
12747#define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
12748#define I2C_SR1_TXE I2C_SR1_TXE_Msk
12749#define I2C_SR1_BERR_Pos (8U)
12750#define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
12751#define I2C_SR1_BERR I2C_SR1_BERR_Msk
12752#define I2C_SR1_ARLO_Pos (9U)
12753#define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
12754#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
12755#define I2C_SR1_AF_Pos (10U)
12756#define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
12757#define I2C_SR1_AF I2C_SR1_AF_Msk
12758#define I2C_SR1_OVR_Pos (11U)
12759#define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
12760#define I2C_SR1_OVR I2C_SR1_OVR_Msk
12761#define I2C_SR1_PECERR_Pos (12U)
12762#define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
12763#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
12764#define I2C_SR1_TIMEOUT_Pos (14U)
12765#define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
12766#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
12767#define I2C_SR1_SMBALERT_Pos (15U)
12768#define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
12769#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
12770
12771/******************* Bit definition for I2C_SR2 register ********************/
12772#define I2C_SR2_MSL_Pos (0U)
12773#define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
12774#define I2C_SR2_MSL I2C_SR2_MSL_Msk
12775#define I2C_SR2_BUSY_Pos (1U)
12776#define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
12777#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
12778#define I2C_SR2_TRA_Pos (2U)
12779#define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
12780#define I2C_SR2_TRA I2C_SR2_TRA_Msk
12781#define I2C_SR2_GENCALL_Pos (4U)
12782#define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
12783#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
12784#define I2C_SR2_SMBDEFAULT_Pos (5U)
12785#define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
12786#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
12787#define I2C_SR2_SMBHOST_Pos (6U)
12788#define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
12789#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
12790#define I2C_SR2_DUALF_Pos (7U)
12791#define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
12792#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
12793#define I2C_SR2_PEC_Pos (8U)
12794#define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
12795#define I2C_SR2_PEC I2C_SR2_PEC_Msk
12796
12797/******************* Bit definition for I2C_CCR register ********************/
12798#define I2C_CCR_CCR_Pos (0U)
12799#define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
12800#define I2C_CCR_CCR I2C_CCR_CCR_Msk
12801#define I2C_CCR_DUTY_Pos (14U)
12802#define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
12803#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
12804#define I2C_CCR_FS_Pos (15U)
12805#define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
12806#define I2C_CCR_FS I2C_CCR_FS_Msk
12807
12808/****************** Bit definition for I2C_TRISE register *******************/
12809#define I2C_TRISE_TRISE_Pos (0U)
12810#define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
12811#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
12812
12813/****************** Bit definition for I2C_FLTR register *******************/
12814#define I2C_FLTR_DNF_Pos (0U)
12815#define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
12816#define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
12817#define I2C_FLTR_ANOFF_Pos (4U)
12818#define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
12819#define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
12820
12821/******************************************************************************/
12822/* */
12823/* Independent WATCHDOG */
12824/* */
12825/******************************************************************************/
12826/******************* Bit definition for IWDG_KR register ********************/
12827#define IWDG_KR_KEY_Pos (0U)
12828#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
12829#define IWDG_KR_KEY IWDG_KR_KEY_Msk
12830
12831/******************* Bit definition for IWDG_PR register ********************/
12832#define IWDG_PR_PR_Pos (0U)
12833#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
12834#define IWDG_PR_PR IWDG_PR_PR_Msk
12835#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
12836#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
12837#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
12838
12839/******************* Bit definition for IWDG_RLR register *******************/
12840#define IWDG_RLR_RL_Pos (0U)
12841#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
12842#define IWDG_RLR_RL IWDG_RLR_RL_Msk
12843
12844/******************* Bit definition for IWDG_SR register ********************/
12845#define IWDG_SR_PVU_Pos (0U)
12846#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
12847#define IWDG_SR_PVU IWDG_SR_PVU_Msk
12848#define IWDG_SR_RVU_Pos (1U)
12849#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
12850#define IWDG_SR_RVU IWDG_SR_RVU_Msk
12851
12852
12853/******************************************************************************/
12854/* */
12855/* LCD-TFT Display Controller (LTDC) */
12856/* */
12857/******************************************************************************/
12858
12859/******************** Bit definition for LTDC_SSCR register *****************/
12860
12861#define LTDC_SSCR_VSH_Pos (0U)
12862#define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos)
12863#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk
12864#define LTDC_SSCR_HSW_Pos (16U)
12865#define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos)
12866#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk
12867
12868/******************** Bit definition for LTDC_BPCR register *****************/
12869
12870#define LTDC_BPCR_AVBP_Pos (0U)
12871#define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos)
12872#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk
12873#define LTDC_BPCR_AHBP_Pos (16U)
12874#define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos)
12875#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk
12876
12877/******************** Bit definition for LTDC_AWCR register *****************/
12878
12879#define LTDC_AWCR_AAH_Pos (0U)
12880#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos)
12881#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk
12882#define LTDC_AWCR_AAW_Pos (16U)
12883#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos)
12884#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk
12885
12886/******************** Bit definition for LTDC_TWCR register *****************/
12887
12888#define LTDC_TWCR_TOTALH_Pos (0U)
12889#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos)
12890#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk
12891#define LTDC_TWCR_TOTALW_Pos (16U)
12892#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos)
12893#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk
12894
12895/******************** Bit definition for LTDC_GCR register ******************/
12896
12897#define LTDC_GCR_LTDCEN_Pos (0U)
12898#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
12899#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk
12900#define LTDC_GCR_DBW_Pos (4U)
12901#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
12902#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk
12903#define LTDC_GCR_DGW_Pos (8U)
12904#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
12905#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk
12906#define LTDC_GCR_DRW_Pos (12U)
12907#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
12908#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk
12909#define LTDC_GCR_DEN_Pos (16U)
12910#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
12911#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk
12912#define LTDC_GCR_PCPOL_Pos (28U)
12913#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
12914#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk
12915#define LTDC_GCR_DEPOL_Pos (29U)
12916#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
12917#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk
12918#define LTDC_GCR_VSPOL_Pos (30U)
12919#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
12920#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk
12921#define LTDC_GCR_HSPOL_Pos (31U)
12922#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
12923#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk
12924
12925/* Legacy defines */
12926#define LTDC_GCR_DTEN LTDC_GCR_DEN
12927
12928/******************** Bit definition for LTDC_SRCR register *****************/
12929
12930#define LTDC_SRCR_IMR_Pos (0U)
12931#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
12932#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk
12933#define LTDC_SRCR_VBR_Pos (1U)
12934#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
12935#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk
12936
12937/******************** Bit definition for LTDC_BCCR register *****************/
12938
12939#define LTDC_BCCR_BCBLUE_Pos (0U)
12940#define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos)
12941#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk
12942#define LTDC_BCCR_BCGREEN_Pos (8U)
12943#define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos)
12944#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk
12945#define LTDC_BCCR_BCRED_Pos (16U)
12946#define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos)
12947#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk
12948
12949/******************** Bit definition for LTDC_IER register ******************/
12950
12951#define LTDC_IER_LIE_Pos (0U)
12952#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
12953#define LTDC_IER_LIE LTDC_IER_LIE_Msk
12954#define LTDC_IER_FUIE_Pos (1U)
12955#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
12956#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk
12957#define LTDC_IER_TERRIE_Pos (2U)
12958#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
12959#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk
12960#define LTDC_IER_RRIE_Pos (3U)
12961#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
12962#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk
12963
12964/******************** Bit definition for LTDC_ISR register ******************/
12965
12966#define LTDC_ISR_LIF_Pos (0U)
12967#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
12968#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk
12969#define LTDC_ISR_FUIF_Pos (1U)
12970#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
12971#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk
12972#define LTDC_ISR_TERRIF_Pos (2U)
12973#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
12974#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk
12975#define LTDC_ISR_RRIF_Pos (3U)
12976#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
12977#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk
12978
12979/******************** Bit definition for LTDC_ICR register ******************/
12980
12981#define LTDC_ICR_CLIF_Pos (0U)
12982#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
12983#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk
12984#define LTDC_ICR_CFUIF_Pos (1U)
12985#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
12986#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk
12987#define LTDC_ICR_CTERRIF_Pos (2U)
12988#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
12989#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk
12990#define LTDC_ICR_CRRIF_Pos (3U)
12991#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
12992#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk
12993
12994/******************** Bit definition for LTDC_LIPCR register ****************/
12995
12996#define LTDC_LIPCR_LIPOS_Pos (0U)
12997#define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)
12998#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk
12999
13000/******************** Bit definition for LTDC_CPSR register *****************/
13001
13002#define LTDC_CPSR_CYPOS_Pos (0U)
13003#define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)
13004#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk
13005#define LTDC_CPSR_CXPOS_Pos (16U)
13006#define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)
13007#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk
13008
13009/******************** Bit definition for LTDC_CDSR register *****************/
13010
13011#define LTDC_CDSR_VDES_Pos (0U)
13012#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
13013#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk
13014#define LTDC_CDSR_HDES_Pos (1U)
13015#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
13016#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk
13017#define LTDC_CDSR_VSYNCS_Pos (2U)
13018#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
13019#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk
13020#define LTDC_CDSR_HSYNCS_Pos (3U)
13021#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
13022#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk
13023
13024/******************** Bit definition for LTDC_LxCR register *****************/
13025
13026#define LTDC_LxCR_LEN_Pos (0U)
13027#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
13028#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk
13029#define LTDC_LxCR_COLKEN_Pos (1U)
13030#define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos)
13031#define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk
13032#define LTDC_LxCR_CLUTEN_Pos (4U)
13033#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
13034#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk
13035
13036/******************** Bit definition for LTDC_LxWHPCR register **************/
13037
13038#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13039#define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)
13040#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk
13041#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13042#define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)
13043#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk
13044
13045/******************** Bit definition for LTDC_LxWVPCR register **************/
13046
13047#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13048#define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)
13049#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk
13050#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13051#define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)
13052#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk
13053
13054/******************** Bit definition for LTDC_LxCKCR register ***************/
13055
13056#define LTDC_LxCKCR_CKBLUE_Pos (0U)
13057#define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)
13058#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk
13059#define LTDC_LxCKCR_CKGREEN_Pos (8U)
13060#define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)
13061#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk
13062#define LTDC_LxCKCR_CKRED_Pos (16U)
13063#define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos)
13064#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk
13065
13066/******************** Bit definition for LTDC_LxPFCR register ***************/
13067
13068#define LTDC_LxPFCR_PF_Pos (0U)
13069#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
13070#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk
13071
13072/******************** Bit definition for LTDC_LxCACR register ***************/
13073
13074#define LTDC_LxCACR_CONSTA_Pos (0U)
13075#define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos)
13076#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk
13077
13078/******************** Bit definition for LTDC_LxDCCR register ***************/
13079
13080#define LTDC_LxDCCR_DCBLUE_Pos (0U)
13081#define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)
13082#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk
13083#define LTDC_LxDCCR_DCGREEN_Pos (8U)
13084#define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)
13085#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk
13086#define LTDC_LxDCCR_DCRED_Pos (16U)
13087#define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos)
13088#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk
13089#define LTDC_LxDCCR_DCALPHA_Pos (24U)
13090#define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)
13091#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk
13092
13093/******************** Bit definition for LTDC_LxBFCR register ***************/
13094
13095#define LTDC_LxBFCR_BF2_Pos (0U)
13096#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
13097#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk
13098#define LTDC_LxBFCR_BF1_Pos (8U)
13099#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
13100#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk
13101
13102/******************** Bit definition for LTDC_LxCFBAR register **************/
13103
13104#define LTDC_LxCFBAR_CFBADD_Pos (0U)
13105#define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos)
13106#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk
13107
13108/******************** Bit definition for LTDC_LxCFBLR register **************/
13109
13110#define LTDC_LxCFBLR_CFBLL_Pos (0U)
13111#define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)
13112#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk
13113#define LTDC_LxCFBLR_CFBP_Pos (16U)
13114#define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)
13115#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk
13116
13117/******************** Bit definition for LTDC_LxCFBLNR register *************/
13118
13119#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13120#define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
13121#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk
13122
13123/******************** Bit definition for LTDC_LxCLUTWR register *************/
13124
13125#define LTDC_LxCLUTWR_BLUE_Pos (0U)
13126#define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)
13127#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk
13128#define LTDC_LxCLUTWR_GREEN_Pos (8U)
13129#define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)
13130#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk
13131#define LTDC_LxCLUTWR_RED_Pos (16U)
13132#define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos)
13133#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk
13134#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13135#define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)
13136#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk
13137
13138
13139/******************************************************************************/
13140/* */
13141/* Power Control */
13142/* */
13143/******************************************************************************/
13144/******************** Bit definition for PWR_CR register ********************/
13145#define PWR_CR_LPDS_Pos (0U)
13146#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
13147#define PWR_CR_LPDS PWR_CR_LPDS_Msk
13148#define PWR_CR_PDDS_Pos (1U)
13149#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
13150#define PWR_CR_PDDS PWR_CR_PDDS_Msk
13151#define PWR_CR_CWUF_Pos (2U)
13152#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
13153#define PWR_CR_CWUF PWR_CR_CWUF_Msk
13154#define PWR_CR_CSBF_Pos (3U)
13155#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
13156#define PWR_CR_CSBF PWR_CR_CSBF_Msk
13157#define PWR_CR_PVDE_Pos (4U)
13158#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
13159#define PWR_CR_PVDE PWR_CR_PVDE_Msk
13160
13161#define PWR_CR_PLS_Pos (5U)
13162#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
13163#define PWR_CR_PLS PWR_CR_PLS_Msk
13164#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
13165#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
13166#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
13167
13169#define PWR_CR_PLS_LEV0 0x00000000U
13170#define PWR_CR_PLS_LEV1 0x00000020U
13171#define PWR_CR_PLS_LEV2 0x00000040U
13172#define PWR_CR_PLS_LEV3 0x00000060U
13173#define PWR_CR_PLS_LEV4 0x00000080U
13174#define PWR_CR_PLS_LEV5 0x000000A0U
13175#define PWR_CR_PLS_LEV6 0x000000C0U
13176#define PWR_CR_PLS_LEV7 0x000000E0U
13177#define PWR_CR_DBP_Pos (8U)
13178#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
13179#define PWR_CR_DBP PWR_CR_DBP_Msk
13180#define PWR_CR_FPDS_Pos (9U)
13181#define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
13182#define PWR_CR_FPDS PWR_CR_FPDS_Msk
13183#define PWR_CR_LPLVDS_Pos (10U)
13184#define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
13185#define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
13186#define PWR_CR_MRLVDS_Pos (11U)
13187#define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
13188#define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
13189#define PWR_CR_ADCDC1_Pos (13U)
13190#define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
13191#define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
13192#define PWR_CR_VOS_Pos (14U)
13193#define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
13194#define PWR_CR_VOS PWR_CR_VOS_Msk
13195#define PWR_CR_VOS_0 0x00004000U
13196#define PWR_CR_VOS_1 0x00008000U
13197#define PWR_CR_ODEN_Pos (16U)
13198#define PWR_CR_ODEN_Msk (0x1UL << PWR_CR_ODEN_Pos)
13199#define PWR_CR_ODEN PWR_CR_ODEN_Msk
13200#define PWR_CR_ODSWEN_Pos (17U)
13201#define PWR_CR_ODSWEN_Msk (0x1UL << PWR_CR_ODSWEN_Pos)
13202#define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk
13203#define PWR_CR_UDEN_Pos (18U)
13204#define PWR_CR_UDEN_Msk (0x3UL << PWR_CR_UDEN_Pos)
13205#define PWR_CR_UDEN PWR_CR_UDEN_Msk
13206#define PWR_CR_UDEN_0 (0x1UL << PWR_CR_UDEN_Pos)
13207#define PWR_CR_UDEN_1 (0x2UL << PWR_CR_UDEN_Pos)
13208
13209/* Legacy define */
13210#define PWR_CR_PMODE PWR_CR_VOS
13211#define PWR_CR_LPUDS PWR_CR_LPLVDS
13212#define PWR_CR_MRUDS PWR_CR_MRLVDS
13213
13214/******************* Bit definition for PWR_CSR register ********************/
13215#define PWR_CSR_WUF_Pos (0U)
13216#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
13217#define PWR_CSR_WUF PWR_CSR_WUF_Msk
13218#define PWR_CSR_SBF_Pos (1U)
13219#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
13220#define PWR_CSR_SBF PWR_CSR_SBF_Msk
13221#define PWR_CSR_PVDO_Pos (2U)
13222#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
13223#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
13224#define PWR_CSR_BRR_Pos (3U)
13225#define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
13226#define PWR_CSR_BRR PWR_CSR_BRR_Msk
13227#define PWR_CSR_EWUP_Pos (8U)
13228#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
13229#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
13230#define PWR_CSR_BRE_Pos (9U)
13231#define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
13232#define PWR_CSR_BRE PWR_CSR_BRE_Msk
13233#define PWR_CSR_VOSRDY_Pos (14U)
13234#define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
13235#define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
13236#define PWR_CSR_ODRDY_Pos (16U)
13237#define PWR_CSR_ODRDY_Msk (0x1UL << PWR_CSR_ODRDY_Pos)
13238#define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk
13239#define PWR_CSR_ODSWRDY_Pos (17U)
13240#define PWR_CSR_ODSWRDY_Msk (0x1UL << PWR_CSR_ODSWRDY_Pos)
13241#define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk
13242#define PWR_CSR_UDRDY_Pos (18U)
13243#define PWR_CSR_UDRDY_Msk (0x3UL << PWR_CSR_UDRDY_Pos)
13244#define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk
13245/* Legacy define */
13246#define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
13247
13248/* Legacy define */
13249#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
13250
13251/******************************************************************************/
13252/* */
13253/* QUADSPI */
13254/* */
13255/******************************************************************************/
13256/***************** Bit definition for QUADSPI_CR register *******************/
13257#define QUADSPI_CR_EN_Pos (0U)
13258#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
13259#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
13260#define QUADSPI_CR_ABORT_Pos (1U)
13261#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
13262#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
13263#define QUADSPI_CR_DMAEN_Pos (2U)
13264#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
13265#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
13266#define QUADSPI_CR_TCEN_Pos (3U)
13267#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
13268#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
13269#define QUADSPI_CR_SSHIFT_Pos (4U)
13270#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
13271#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
13272#define QUADSPI_CR_DFM_Pos (6U)
13273#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
13274#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
13275#define QUADSPI_CR_FSEL_Pos (7U)
13276#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
13277#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
13278#define QUADSPI_CR_FTHRES_Pos (8U)
13279#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
13280#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
13281#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
13282#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
13283#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
13284#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
13285#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
13286#define QUADSPI_CR_TEIE_Pos (16U)
13287#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
13288#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
13289#define QUADSPI_CR_TCIE_Pos (17U)
13290#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
13291#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
13292#define QUADSPI_CR_FTIE_Pos (18U)
13293#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
13294#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
13295#define QUADSPI_CR_SMIE_Pos (19U)
13296#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
13297#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
13298#define QUADSPI_CR_TOIE_Pos (20U)
13299#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
13300#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
13301#define QUADSPI_CR_APMS_Pos (22U)
13302#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
13303#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
13304#define QUADSPI_CR_PMM_Pos (23U)
13305#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
13306#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
13307#define QUADSPI_CR_PRESCALER_Pos (24U)
13308#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
13309#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
13310#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
13311#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
13312#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
13313#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
13314#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
13315#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
13316#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
13317#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
13318
13319/***************** Bit definition for QUADSPI_DCR register ******************/
13320#define QUADSPI_DCR_CKMODE_Pos (0U)
13321#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
13322#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
13323#define QUADSPI_DCR_CSHT_Pos (8U)
13324#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
13325#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
13326#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
13327#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
13328#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
13329#define QUADSPI_DCR_FSIZE_Pos (16U)
13330#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
13331#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
13332#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
13333#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
13334#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
13335#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
13336#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
13337
13338/****************** Bit definition for QUADSPI_SR register *******************/
13339#define QUADSPI_SR_TEF_Pos (0U)
13340#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
13341#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
13342#define QUADSPI_SR_TCF_Pos (1U)
13343#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
13344#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
13345#define QUADSPI_SR_FTF_Pos (2U)
13346#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
13347#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
13348#define QUADSPI_SR_SMF_Pos (3U)
13349#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
13350#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
13351#define QUADSPI_SR_TOF_Pos (4U)
13352#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
13353#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
13354#define QUADSPI_SR_BUSY_Pos (5U)
13355#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
13356#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
13357#define QUADSPI_SR_FLEVEL_Pos (8U)
13358#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
13359#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
13360#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
13361#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
13362#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
13363#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
13364#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
13365#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
13366
13367/****************** Bit definition for QUADSPI_FCR register ******************/
13368#define QUADSPI_FCR_CTEF_Pos (0U)
13369#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
13370#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
13371#define QUADSPI_FCR_CTCF_Pos (1U)
13372#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
13373#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
13374#define QUADSPI_FCR_CSMF_Pos (3U)
13375#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
13376#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
13377#define QUADSPI_FCR_CTOF_Pos (4U)
13378#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
13379#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
13380
13381/****************** Bit definition for QUADSPI_DLR register ******************/
13382#define QUADSPI_DLR_DL_Pos (0U)
13383#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
13384#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
13385
13386/****************** Bit definition for QUADSPI_CCR register ******************/
13387#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13388#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
13389#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
13390#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
13391#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
13392#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
13393#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
13394#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
13395#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
13396#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
13397#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
13398#define QUADSPI_CCR_IMODE_Pos (8U)
13399#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
13400#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
13401#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
13402#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
13403#define QUADSPI_CCR_ADMODE_Pos (10U)
13404#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
13405#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
13406#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
13407#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
13408#define QUADSPI_CCR_ADSIZE_Pos (12U)
13409#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
13410#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
13411#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
13412#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
13413#define QUADSPI_CCR_ABMODE_Pos (14U)
13414#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
13415#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
13416#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
13417#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
13418#define QUADSPI_CCR_ABSIZE_Pos (16U)
13419#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
13420#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
13421#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
13422#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
13423#define QUADSPI_CCR_DCYC_Pos (18U)
13424#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
13425#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
13426#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
13427#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
13428#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
13429#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
13430#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
13431#define QUADSPI_CCR_DMODE_Pos (24U)
13432#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
13433#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
13434#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
13435#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
13436#define QUADSPI_CCR_FMODE_Pos (26U)
13437#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
13438#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
13439#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
13440#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
13441#define QUADSPI_CCR_SIOO_Pos (28U)
13442#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
13443#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
13444#define QUADSPI_CCR_DHHC_Pos (30U)
13445#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
13446#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
13447#define QUADSPI_CCR_DDRM_Pos (31U)
13448#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
13449#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
13450/****************** Bit definition for QUADSPI_AR register *******************/
13451#define QUADSPI_AR_ADDRESS_Pos (0U)
13452#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
13453#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
13454
13455/****************** Bit definition for QUADSPI_ABR register ******************/
13456#define QUADSPI_ABR_ALTERNATE_Pos (0U)
13457#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
13458#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
13459
13460/****************** Bit definition for QUADSPI_DR register *******************/
13461#define QUADSPI_DR_DATA_Pos (0U)
13462#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
13463#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
13464
13465/****************** Bit definition for QUADSPI_PSMKR register ****************/
13466#define QUADSPI_PSMKR_MASK_Pos (0U)
13467#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
13468#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
13469
13470/****************** Bit definition for QUADSPI_PSMAR register ****************/
13471#define QUADSPI_PSMAR_MATCH_Pos (0U)
13472#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
13473#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
13474
13475/****************** Bit definition for QUADSPI_PIR register *****************/
13476#define QUADSPI_PIR_INTERVAL_Pos (0U)
13477#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
13478#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
13479
13480/****************** Bit definition for QUADSPI_LPTR register *****************/
13481#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13482#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
13483#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
13484
13485/******************************************************************************/
13486/* */
13487/* Reset and Clock Control */
13488/* */
13489/******************************************************************************/
13490/******************** Bit definition for RCC_CR register ********************/
13491#define RCC_CR_HSION_Pos (0U)
13492#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
13493#define RCC_CR_HSION RCC_CR_HSION_Msk
13494#define RCC_CR_HSIRDY_Pos (1U)
13495#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
13496#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13497
13498#define RCC_CR_HSITRIM_Pos (3U)
13499#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
13500#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
13501#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
13502#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
13503#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
13504#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
13505#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
13506
13507#define RCC_CR_HSICAL_Pos (8U)
13508#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
13509#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
13510#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
13511#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
13512#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
13513#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
13514#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
13515#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
13516#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
13517#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
13518
13519#define RCC_CR_HSEON_Pos (16U)
13520#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
13521#define RCC_CR_HSEON RCC_CR_HSEON_Msk
13522#define RCC_CR_HSERDY_Pos (17U)
13523#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
13524#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13525#define RCC_CR_HSEBYP_Pos (18U)
13526#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
13527#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13528#define RCC_CR_CSSON_Pos (19U)
13529#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
13530#define RCC_CR_CSSON RCC_CR_CSSON_Msk
13531#define RCC_CR_PLLON_Pos (24U)
13532#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
13533#define RCC_CR_PLLON RCC_CR_PLLON_Msk
13534#define RCC_CR_PLLRDY_Pos (25U)
13535#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
13536#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13537/*
13538 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
13539 */
13540#define RCC_PLLI2S_SUPPORT
13541
13542#define RCC_CR_PLLI2SON_Pos (26U)
13543#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
13544#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
13545#define RCC_CR_PLLI2SRDY_Pos (27U)
13546#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
13547#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
13548/*
13549 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
13550 */
13551#define RCC_PLLSAI_SUPPORT
13552
13553#define RCC_CR_PLLSAION_Pos (28U)
13554#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
13555#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
13556#define RCC_CR_PLLSAIRDY_Pos (29U)
13557#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
13558#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
13559
13560/******************** Bit definition for RCC_PLLCFGR register ***************/
13561#define RCC_PLLCFGR_PLLM_Pos (0U)
13562#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
13563#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
13564#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
13565#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
13566#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
13567#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
13568#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
13569#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
13570
13571#define RCC_PLLCFGR_PLLN_Pos (6U)
13572#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
13573#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
13574#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
13575#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
13576#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
13577#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
13578#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
13579#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
13580#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
13581#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
13582#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
13583
13584#define RCC_PLLCFGR_PLLP_Pos (16U)
13585#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
13586#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
13587#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
13588#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
13589
13590#define RCC_PLLCFGR_PLLSRC_Pos (22U)
13591#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
13592#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
13593#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
13594#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
13595#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
13596#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
13597
13598#define RCC_PLLCFGR_PLLQ_Pos (24U)
13599#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
13600#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
13601#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
13602#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
13603#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
13604#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
13605
13606#define RCC_PLLCFGR_PLLR_Pos (28U)
13607#define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos)
13608#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
13609#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos)
13610#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos)
13611#define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos)
13612
13613/******************** Bit definition for RCC_CFGR register ******************/
13615#define RCC_CFGR_SW_Pos (0U)
13616#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
13617#define RCC_CFGR_SW RCC_CFGR_SW_Msk
13618#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
13619#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
13620
13621#define RCC_CFGR_SW_HSI 0x00000000U
13622#define RCC_CFGR_SW_HSE 0x00000001U
13623#define RCC_CFGR_SW_PLL 0x00000002U
13624
13626#define RCC_CFGR_SWS_Pos (2U)
13627#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
13628#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
13629#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
13630#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
13631
13632#define RCC_CFGR_SWS_HSI 0x00000000U
13633#define RCC_CFGR_SWS_HSE 0x00000004U
13634#define RCC_CFGR_SWS_PLL 0x00000008U
13635
13637#define RCC_CFGR_HPRE_Pos (4U)
13638#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
13639#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
13640#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
13641#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
13642#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
13643#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
13644
13645#define RCC_CFGR_HPRE_DIV1 0x00000000U
13646#define RCC_CFGR_HPRE_DIV2 0x00000080U
13647#define RCC_CFGR_HPRE_DIV4 0x00000090U
13648#define RCC_CFGR_HPRE_DIV8 0x000000A0U
13649#define RCC_CFGR_HPRE_DIV16 0x000000B0U
13650#define RCC_CFGR_HPRE_DIV64 0x000000C0U
13651#define RCC_CFGR_HPRE_DIV128 0x000000D0U
13652#define RCC_CFGR_HPRE_DIV256 0x000000E0U
13653#define RCC_CFGR_HPRE_DIV512 0x000000F0U
13654
13656#define RCC_CFGR_PPRE1_Pos (10U)
13657#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
13658#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
13659#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
13660#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
13661#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
13662
13663#define RCC_CFGR_PPRE1_DIV1 0x00000000U
13664#define RCC_CFGR_PPRE1_DIV2 0x00001000U
13665#define RCC_CFGR_PPRE1_DIV4 0x00001400U
13666#define RCC_CFGR_PPRE1_DIV8 0x00001800U
13667#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
13668
13670#define RCC_CFGR_PPRE2_Pos (13U)
13671#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
13672#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
13673#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
13674#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
13675#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
13676
13677#define RCC_CFGR_PPRE2_DIV1 0x00000000U
13678#define RCC_CFGR_PPRE2_DIV2 0x00008000U
13679#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
13680#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
13681#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
13682
13684#define RCC_CFGR_RTCPRE_Pos (16U)
13685#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
13686#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13687#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
13688#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
13689#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
13690#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
13691#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
13692
13694#define RCC_CFGR_MCO1_Pos (21U)
13695#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
13696#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13697#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
13698#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
13699
13700#define RCC_CFGR_I2SSRC_Pos (23U)
13701#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
13702#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
13703
13704#define RCC_CFGR_MCO1PRE_Pos (24U)
13705#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
13706#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13707#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
13708#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
13709#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
13710
13711#define RCC_CFGR_MCO2PRE_Pos (27U)
13712#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
13713#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13714#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
13715#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
13716#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
13717
13718#define RCC_CFGR_MCO2_Pos (30U)
13719#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
13720#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13721#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
13722#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
13723
13724/******************** Bit definition for RCC_CIR register *******************/
13725#define RCC_CIR_LSIRDYF_Pos (0U)
13726#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
13727#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
13728#define RCC_CIR_LSERDYF_Pos (1U)
13729#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
13730#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
13731#define RCC_CIR_HSIRDYF_Pos (2U)
13732#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
13733#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
13734#define RCC_CIR_HSERDYF_Pos (3U)
13735#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
13736#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
13737#define RCC_CIR_PLLRDYF_Pos (4U)
13738#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
13739#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
13740#define RCC_CIR_PLLI2SRDYF_Pos (5U)
13741#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
13742#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
13743
13744#define RCC_CIR_PLLSAIRDYF_Pos (6U)
13745#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
13746#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
13747#define RCC_CIR_CSSF_Pos (7U)
13748#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
13749#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
13750#define RCC_CIR_LSIRDYIE_Pos (8U)
13751#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
13752#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
13753#define RCC_CIR_LSERDYIE_Pos (9U)
13754#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
13755#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
13756#define RCC_CIR_HSIRDYIE_Pos (10U)
13757#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
13758#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
13759#define RCC_CIR_HSERDYIE_Pos (11U)
13760#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
13761#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
13762#define RCC_CIR_PLLRDYIE_Pos (12U)
13763#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
13764#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
13765#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
13766#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
13767#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
13768
13769#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
13770#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
13771#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
13772#define RCC_CIR_LSIRDYC_Pos (16U)
13773#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
13774#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
13775#define RCC_CIR_LSERDYC_Pos (17U)
13776#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
13777#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
13778#define RCC_CIR_HSIRDYC_Pos (18U)
13779#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
13780#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
13781#define RCC_CIR_HSERDYC_Pos (19U)
13782#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
13783#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
13784#define RCC_CIR_PLLRDYC_Pos (20U)
13785#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
13786#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
13787#define RCC_CIR_PLLI2SRDYC_Pos (21U)
13788#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
13789#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
13790#define RCC_CIR_PLLSAIRDYC_Pos (22U)
13791#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
13792#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
13793
13794#define RCC_CIR_CSSC_Pos (23U)
13795#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
13796#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
13797
13798/******************** Bit definition for RCC_AHB1RSTR register **************/
13799#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
13800#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
13801#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
13802#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
13803#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
13804#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
13805#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
13806#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
13807#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
13808#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
13809#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
13810#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
13811#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
13812#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
13813#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
13814#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
13815#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
13816#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
13817#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
13818#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
13819#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
13820#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
13821#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
13822#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
13823#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
13824#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
13825#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
13826#define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
13827#define RCC_AHB1RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOJRST_Pos)
13828#define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
13829#define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
13830#define RCC_AHB1RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOKRST_Pos)
13831#define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
13832#define RCC_AHB1RSTR_CRCRST_Pos (12U)
13833#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
13834#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
13835#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
13836#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
13837#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
13838#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
13839#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
13840#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
13841#define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
13842#define RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos)
13843#define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
13844#define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
13845#define RCC_AHB1RSTR_ETHMACRST_Msk (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos)
13846#define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
13847#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
13848#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
13849#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
13850
13851/******************** Bit definition for RCC_AHB2RSTR register **************/
13852#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
13853#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
13854#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
13855#define RCC_AHB2RSTR_RNGRST_Pos (6U)
13856#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
13857#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
13858#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
13859#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
13860#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
13861/******************** Bit definition for RCC_AHB3RSTR register **************/
13862#define RCC_AHB3RSTR_FMCRST_Pos (0U)
13863#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
13864#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
13865#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
13866#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
13867#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
13868
13869
13870/******************** Bit definition for RCC_APB1RSTR register **************/
13871#define RCC_APB1RSTR_TIM2RST_Pos (0U)
13872#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
13873#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
13874#define RCC_APB1RSTR_TIM3RST_Pos (1U)
13875#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
13876#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
13877#define RCC_APB1RSTR_TIM4RST_Pos (2U)
13878#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
13879#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
13880#define RCC_APB1RSTR_TIM5RST_Pos (3U)
13881#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
13882#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
13883#define RCC_APB1RSTR_TIM6RST_Pos (4U)
13884#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
13885#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
13886#define RCC_APB1RSTR_TIM7RST_Pos (5U)
13887#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
13888#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
13889#define RCC_APB1RSTR_TIM12RST_Pos (6U)
13890#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
13891#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
13892#define RCC_APB1RSTR_TIM13RST_Pos (7U)
13893#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
13894#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
13895#define RCC_APB1RSTR_TIM14RST_Pos (8U)
13896#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
13897#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
13898#define RCC_APB1RSTR_WWDGRST_Pos (11U)
13899#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
13900#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
13901#define RCC_APB1RSTR_SPI2RST_Pos (14U)
13902#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
13903#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
13904#define RCC_APB1RSTR_SPI3RST_Pos (15U)
13905#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
13906#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
13907#define RCC_APB1RSTR_USART2RST_Pos (17U)
13908#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
13909#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
13910#define RCC_APB1RSTR_USART3RST_Pos (18U)
13911#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
13912#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
13913#define RCC_APB1RSTR_UART4RST_Pos (19U)
13914#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
13915#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
13916#define RCC_APB1RSTR_UART5RST_Pos (20U)
13917#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
13918#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
13919#define RCC_APB1RSTR_I2C1RST_Pos (21U)
13920#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
13921#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
13922#define RCC_APB1RSTR_I2C2RST_Pos (22U)
13923#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
13924#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
13925#define RCC_APB1RSTR_I2C3RST_Pos (23U)
13926#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
13927#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
13928#define RCC_APB1RSTR_CAN1RST_Pos (25U)
13929#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
13930#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
13931#define RCC_APB1RSTR_CAN2RST_Pos (26U)
13932#define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)
13933#define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
13934#define RCC_APB1RSTR_PWRRST_Pos (28U)
13935#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
13936#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
13937#define RCC_APB1RSTR_DACRST_Pos (29U)
13938#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
13939#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
13940#define RCC_APB1RSTR_UART7RST_Pos (30U)
13941#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
13942#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
13943#define RCC_APB1RSTR_UART8RST_Pos (31U)
13944#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
13945#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
13946
13947/******************** Bit definition for RCC_APB2RSTR register **************/
13948#define RCC_APB2RSTR_TIM1RST_Pos (0U)
13949#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
13950#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
13951#define RCC_APB2RSTR_TIM8RST_Pos (1U)
13952#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
13953#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
13954#define RCC_APB2RSTR_USART1RST_Pos (4U)
13955#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
13956#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
13957#define RCC_APB2RSTR_USART6RST_Pos (5U)
13958#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
13959#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
13960#define RCC_APB2RSTR_ADCRST_Pos (8U)
13961#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
13962#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
13963#define RCC_APB2RSTR_SDIORST_Pos (11U)
13964#define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
13965#define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
13966#define RCC_APB2RSTR_SPI1RST_Pos (12U)
13967#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
13968#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
13969#define RCC_APB2RSTR_SPI4RST_Pos (13U)
13970#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
13971#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
13972#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
13973#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
13974#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
13975#define RCC_APB2RSTR_TIM9RST_Pos (16U)
13976#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
13977#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
13978#define RCC_APB2RSTR_TIM10RST_Pos (17U)
13979#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
13980#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
13981#define RCC_APB2RSTR_TIM11RST_Pos (18U)
13982#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
13983#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
13984#define RCC_APB2RSTR_SPI5RST_Pos (20U)
13985#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
13986#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
13987#define RCC_APB2RSTR_SPI6RST_Pos (21U)
13988#define RCC_APB2RSTR_SPI6RST_Msk (0x1UL << RCC_APB2RSTR_SPI6RST_Pos)
13989#define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
13990#define RCC_APB2RSTR_SAI1RST_Pos (22U)
13991#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
13992#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
13993#define RCC_APB2RSTR_LTDCRST_Pos (26U)
13994#define RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos)
13995#define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
13996#define RCC_APB2RSTR_DSIRST_Pos (27U)
13997#define RCC_APB2RSTR_DSIRST_Msk (0x1UL << RCC_APB2RSTR_DSIRST_Pos)
13998#define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
13999
14000/* Old SPI1RST bit definition, maintained for legacy purpose */
14001#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
14002
14003/******************** Bit definition for RCC_AHB1ENR register ***************/
14004#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
14005#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
14006#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
14007#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
14008#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
14009#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
14010#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
14011#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
14012#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
14013#define RCC_AHB1ENR_GPIODEN_Pos (3U)
14014#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
14015#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
14016#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
14017#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
14018#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
14019#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
14020#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
14021#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
14022#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
14023#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
14024#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
14025#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
14026#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
14027#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
14028#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
14029#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
14030#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
14031#define RCC_AHB1ENR_GPIOJEN_Pos (9U)
14032#define RCC_AHB1ENR_GPIOJEN_Msk (0x1UL << RCC_AHB1ENR_GPIOJEN_Pos)
14033#define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
14034#define RCC_AHB1ENR_GPIOKEN_Pos (10U)
14035#define RCC_AHB1ENR_GPIOKEN_Msk (0x1UL << RCC_AHB1ENR_GPIOKEN_Pos)
14036#define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
14037#define RCC_AHB1ENR_CRCEN_Pos (12U)
14038#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
14039#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
14040#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
14041#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
14042#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
14043#define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
14044#define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos)
14045#define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
14046#define RCC_AHB1ENR_DMA1EN_Pos (21U)
14047#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
14048#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14049#define RCC_AHB1ENR_DMA2EN_Pos (22U)
14050#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
14051#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14052#define RCC_AHB1ENR_DMA2DEN_Pos (23U)
14053#define RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos)
14054#define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
14055#define RCC_AHB1ENR_ETHMACEN_Pos (25U)
14056#define RCC_AHB1ENR_ETHMACEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)
14057#define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
14058#define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
14059#define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos)
14060#define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
14061#define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
14062#define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos)
14063#define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
14064#define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
14065#define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos)
14066#define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
14067#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
14068#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
14069#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
14070#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
14071#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
14072#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
14073/******************** Bit definition for RCC_AHB2ENR register ***************/
14074/*
14075 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
14076 */
14077#define RCC_AHB2_SUPPORT
14078
14079#define RCC_AHB2ENR_DCMIEN_Pos (0U)
14080#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
14081#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14082#define RCC_AHB2ENR_RNGEN_Pos (6U)
14083#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
14084#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14085#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
14086#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
14087#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
14088
14089/******************** Bit definition for RCC_AHB3ENR register ***************/
14090/*
14091 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
14092 */
14093#define RCC_AHB3_SUPPORT
14094
14095#define RCC_AHB3ENR_FMCEN_Pos (0U)
14096#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
14097#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14098#define RCC_AHB3ENR_QSPIEN_Pos (1U)
14099#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
14100#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14101
14102/******************** Bit definition for RCC_APB1ENR register ***************/
14103#define RCC_APB1ENR_TIM2EN_Pos (0U)
14104#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
14105#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
14106#define RCC_APB1ENR_TIM3EN_Pos (1U)
14107#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
14108#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
14109#define RCC_APB1ENR_TIM4EN_Pos (2U)
14110#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
14111#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
14112#define RCC_APB1ENR_TIM5EN_Pos (3U)
14113#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
14114#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
14115#define RCC_APB1ENR_TIM6EN_Pos (4U)
14116#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
14117#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
14118#define RCC_APB1ENR_TIM7EN_Pos (5U)
14119#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
14120#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
14121#define RCC_APB1ENR_TIM12EN_Pos (6U)
14122#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
14123#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
14124#define RCC_APB1ENR_TIM13EN_Pos (7U)
14125#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
14126#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
14127#define RCC_APB1ENR_TIM14EN_Pos (8U)
14128#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
14129#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
14130#define RCC_APB1ENR_WWDGEN_Pos (11U)
14131#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
14132#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
14133#define RCC_APB1ENR_SPI2EN_Pos (14U)
14134#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
14135#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
14136#define RCC_APB1ENR_SPI3EN_Pos (15U)
14137#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
14138#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
14139#define RCC_APB1ENR_USART2EN_Pos (17U)
14140#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
14141#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
14142#define RCC_APB1ENR_USART3EN_Pos (18U)
14143#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
14144#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
14145#define RCC_APB1ENR_UART4EN_Pos (19U)
14146#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
14147#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
14148#define RCC_APB1ENR_UART5EN_Pos (20U)
14149#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
14150#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
14151#define RCC_APB1ENR_I2C1EN_Pos (21U)
14152#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
14153#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
14154#define RCC_APB1ENR_I2C2EN_Pos (22U)
14155#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
14156#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
14157#define RCC_APB1ENR_I2C3EN_Pos (23U)
14158#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
14159#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
14160#define RCC_APB1ENR_CAN1EN_Pos (25U)
14161#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
14162#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
14163#define RCC_APB1ENR_CAN2EN_Pos (26U)
14164#define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)
14165#define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
14166#define RCC_APB1ENR_PWREN_Pos (28U)
14167#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
14168#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
14169#define RCC_APB1ENR_DACEN_Pos (29U)
14170#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
14171#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
14172#define RCC_APB1ENR_UART7EN_Pos (30U)
14173#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
14174#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
14175#define RCC_APB1ENR_UART8EN_Pos (31U)
14176#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
14177#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
14178
14179/******************** Bit definition for RCC_APB2ENR register ***************/
14180#define RCC_APB2ENR_TIM1EN_Pos (0U)
14181#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
14182#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14183#define RCC_APB2ENR_TIM8EN_Pos (1U)
14184#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
14185#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14186#define RCC_APB2ENR_USART1EN_Pos (4U)
14187#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
14188#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14189#define RCC_APB2ENR_USART6EN_Pos (5U)
14190#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
14191#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14192#define RCC_APB2ENR_ADC1EN_Pos (8U)
14193#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
14194#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
14195#define RCC_APB2ENR_ADC2EN_Pos (9U)
14196#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
14197#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
14198#define RCC_APB2ENR_ADC3EN_Pos (10U)
14199#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
14200#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
14201#define RCC_APB2ENR_SDIOEN_Pos (11U)
14202#define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
14203#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
14204#define RCC_APB2ENR_SPI1EN_Pos (12U)
14205#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
14206#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14207#define RCC_APB2ENR_SPI4EN_Pos (13U)
14208#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
14209#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14210#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
14211#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
14212#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
14213#define RCC_APB2ENR_TIM9EN_Pos (16U)
14214#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
14215#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
14216#define RCC_APB2ENR_TIM10EN_Pos (17U)
14217#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
14218#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
14219#define RCC_APB2ENR_TIM11EN_Pos (18U)
14220#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
14221#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
14222#define RCC_APB2ENR_SPI5EN_Pos (20U)
14223#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
14224#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14225#define RCC_APB2ENR_SPI6EN_Pos (21U)
14226#define RCC_APB2ENR_SPI6EN_Msk (0x1UL << RCC_APB2ENR_SPI6EN_Pos)
14227#define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
14228#define RCC_APB2ENR_SAI1EN_Pos (22U)
14229#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
14230#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14231#define RCC_APB2ENR_LTDCEN_Pos (26U)
14232#define RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos)
14233#define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
14234#define RCC_APB2ENR_DSIEN_Pos (27U)
14235#define RCC_APB2ENR_DSIEN_Msk (0x1UL << RCC_APB2ENR_DSIEN_Pos)
14236#define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
14237
14238/******************** Bit definition for RCC_AHB1LPENR register *************/
14239#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
14240#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
14241#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
14242#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
14243#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
14244#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
14245#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
14246#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
14247#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
14248#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
14249#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
14250#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
14251#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
14252#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
14253#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
14254#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
14255#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
14256#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
14257#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
14258#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
14259#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
14260#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
14261#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
14262#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
14263#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
14264#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
14265#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
14266#define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
14267#define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOJLPEN_Pos)
14268#define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
14269#define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
14270#define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOKLPEN_Pos)
14271#define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
14272#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
14273#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
14274#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14275#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
14276#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
14277#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
14278#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
14279#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
14280#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
14281#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
14282#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
14283#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
14284#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
14285#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
14286#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14287#define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
14288#define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM3LPEN_Pos)
14289#define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
14290#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
14291#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
14292#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14293#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
14294#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
14295#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14296#define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
14297#define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2DLPEN_Pos)
14298#define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
14299
14300#define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
14301#define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos)
14302#define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
14303#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
14304#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos)
14305#define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14306#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
14307#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos)
14308#define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14309#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
14310#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos)
14311#define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14312#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
14313#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
14314#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
14315#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
14316#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
14317#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14318
14319/******************** Bit definition for RCC_AHB2LPENR register *************/
14320#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
14321#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
14322#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
14323#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14324#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
14325#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14326#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
14327#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
14328#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
14329
14330/******************** Bit definition for RCC_AHB3LPENR register *************/
14331#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
14332#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
14333#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14334#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
14335#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
14336#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
14337
14338/******************** Bit definition for RCC_APB1LPENR register *************/
14339#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
14340#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
14341#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
14342#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
14343#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
14344#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
14345#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
14346#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
14347#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
14348#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
14349#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
14350#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
14351#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
14352#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
14353#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
14354#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
14355#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
14356#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
14357#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
14358#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
14359#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
14360#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
14361#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
14362#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
14363#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
14364#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
14365#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
14366#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
14367#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
14368#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
14369#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
14370#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
14371#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
14372#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
14373#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
14374#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
14375#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
14376#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
14377#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
14378#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
14379#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
14380#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
14381#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
14382#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
14383#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
14384#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
14385#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
14386#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
14387#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
14388#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
14389#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
14390#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
14391#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
14392#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
14393#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
14394#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
14395#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
14396#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
14397#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
14398#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
14399#define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
14400#define RCC_APB1LPENR_CAN2LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos)
14401#define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
14402#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
14403#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
14404#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
14405#define RCC_APB1LPENR_DACLPEN_Pos (29U)
14406#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
14407#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
14408#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
14409#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
14410#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
14411#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
14412#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
14413#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
14414
14415/******************** Bit definition for RCC_APB2LPENR register *************/
14416#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14417#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
14418#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14419#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14420#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
14421#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14422#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14423#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
14424#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14425#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14426#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
14427#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14428#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
14429#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
14430#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
14431#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
14432#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
14433#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
14434#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
14435#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
14436#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
14437#define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
14438#define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
14439#define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
14440#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14441#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
14442#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14443#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14444#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
14445#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14446#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
14447#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
14448#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
14449#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
14450#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
14451#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
14452#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
14453#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
14454#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
14455#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
14456#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
14457#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
14458#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14459#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
14460#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14461#define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
14462#define RCC_APB2LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI6LPEN_Pos)
14463#define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
14464#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14465#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
14466#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14467#define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
14468#define RCC_APB2LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB2LPENR_LTDCLPEN_Pos)
14469#define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
14470#define RCC_APB2LPENR_DSILPEN_Pos (27U)
14471#define RCC_APB2LPENR_DSILPEN_Msk (0x1UL << RCC_APB2LPENR_DSILPEN_Pos)
14472#define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
14473
14474/******************** Bit definition for RCC_BDCR register ******************/
14475#define RCC_BDCR_LSEON_Pos (0U)
14476#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
14477#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14478#define RCC_BDCR_LSERDY_Pos (1U)
14479#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
14480#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14481#define RCC_BDCR_LSEBYP_Pos (2U)
14482#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
14483#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14484#define RCC_BDCR_LSEMOD_Pos (3U)
14485#define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
14486#define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
14487
14488#define RCC_BDCR_RTCSEL_Pos (8U)
14489#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
14490#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14491#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
14492#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
14493
14494#define RCC_BDCR_RTCEN_Pos (15U)
14495#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
14496#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14497#define RCC_BDCR_BDRST_Pos (16U)
14498#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
14499#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14500
14501/******************** Bit definition for RCC_CSR register *******************/
14502#define RCC_CSR_LSION_Pos (0U)
14503#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
14504#define RCC_CSR_LSION RCC_CSR_LSION_Msk
14505#define RCC_CSR_LSIRDY_Pos (1U)
14506#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
14507#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14508#define RCC_CSR_RMVF_Pos (24U)
14509#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
14510#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
14511#define RCC_CSR_BORRSTF_Pos (25U)
14512#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
14513#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
14514#define RCC_CSR_PINRSTF_Pos (26U)
14515#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
14516#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
14517#define RCC_CSR_PORRSTF_Pos (27U)
14518#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
14519#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
14520#define RCC_CSR_SFTRSTF_Pos (28U)
14521#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
14522#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
14523#define RCC_CSR_IWDGRSTF_Pos (29U)
14524#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
14525#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
14526#define RCC_CSR_WWDGRSTF_Pos (30U)
14527#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
14528#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
14529#define RCC_CSR_LPWRRSTF_Pos (31U)
14530#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
14531#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
14532/* Legacy defines */
14533#define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
14534#define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
14535
14536/******************** Bit definition for RCC_SSCGR register *****************/
14537#define RCC_SSCGR_MODPER_Pos (0U)
14538#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
14539#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
14540#define RCC_SSCGR_INCSTEP_Pos (13U)
14541#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
14542#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
14543#define RCC_SSCGR_SPREADSEL_Pos (30U)
14544#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
14545#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
14546#define RCC_SSCGR_SSCGEN_Pos (31U)
14547#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
14548#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
14549
14550/******************** Bit definition for RCC_PLLI2SCFGR register ************/
14551#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
14552#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14553#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
14554#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14555#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14556#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14557#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14558#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14559#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14560#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14561#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14562#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
14563
14564#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
14565#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14566#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
14567#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14568#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14569#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14570#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
14571#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
14572#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14573#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
14574#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14575#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14576#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
14577
14578/******************** Bit definition for RCC_PLLSAICFGR register ************/
14579#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
14580#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14581#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
14582#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14583#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14584#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14585#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14586#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14587#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14588#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14589#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14590#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
14591
14592#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
14593#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14594#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
14595#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14596#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
14597
14598#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
14599#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14600#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
14601#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14602#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14603#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14604#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
14605
14606#define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
14607#define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14608#define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
14609#define RCC_PLLSAICFGR_PLLSAIR_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14610#define RCC_PLLSAICFGR_PLLSAIR_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14611#define RCC_PLLSAICFGR_PLLSAIR_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIR_Pos)
14612
14613/******************** Bit definition for RCC_DCKCFGR register ***************/
14614#define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
14615#define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14616#define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
14617#define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14618#define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14619#define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14620#define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14621#define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLI2SDIVQ_Pos)
14622
14623#define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
14624#define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14625#define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
14626#define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14627#define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14628#define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14629#define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14630#define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR_PLLSAIDIVQ_Pos)
14631#define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
14632#define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14633#define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
14634#define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14635#define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2UL << RCC_DCKCFGR_PLLSAIDIVR_Pos)
14636
14637#define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
14638#define RCC_DCKCFGR_SAI1ASRC_Msk (0x3UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14639#define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
14640#define RCC_DCKCFGR_SAI1ASRC_0 (0x1UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14641#define RCC_DCKCFGR_SAI1ASRC_1 (0x2UL << RCC_DCKCFGR_SAI1ASRC_Pos)
14642#define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
14643#define RCC_DCKCFGR_SAI1BSRC_Msk (0x3UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14644#define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
14645#define RCC_DCKCFGR_SAI1BSRC_0 (0x1UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14646#define RCC_DCKCFGR_SAI1BSRC_1 (0x2UL << RCC_DCKCFGR_SAI1BSRC_Pos)
14647#define RCC_DCKCFGR_TIMPRE_Pos (24U)
14648#define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
14649#define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
14650#define RCC_DCKCFGR_CK48MSEL_Pos (27U)
14651#define RCC_DCKCFGR_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR_CK48MSEL_Pos)
14652#define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
14653#define RCC_DCKCFGR_SDIOSEL_Pos (28U)
14654#define RCC_DCKCFGR_SDIOSEL_Msk (0x1UL << RCC_DCKCFGR_SDIOSEL_Pos)
14655#define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
14656#define RCC_DCKCFGR_DSISEL_Pos (29U)
14657#define RCC_DCKCFGR_DSISEL_Msk (0x1UL << RCC_DCKCFGR_DSISEL_Pos)
14658#define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
14659
14660
14661/******************************************************************************/
14662/* */
14663/* RNG */
14664/* */
14665/******************************************************************************/
14666/******************** Bits definition for RNG_CR register *******************/
14667#define RNG_CR_RNGEN_Pos (2U)
14668#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
14669#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14670#define RNG_CR_IE_Pos (3U)
14671#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
14672#define RNG_CR_IE RNG_CR_IE_Msk
14673
14674/******************** Bits definition for RNG_SR register *******************/
14675#define RNG_SR_DRDY_Pos (0U)
14676#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
14677#define RNG_SR_DRDY RNG_SR_DRDY_Msk
14678#define RNG_SR_CECS_Pos (1U)
14679#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
14680#define RNG_SR_CECS RNG_SR_CECS_Msk
14681#define RNG_SR_SECS_Pos (2U)
14682#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
14683#define RNG_SR_SECS RNG_SR_SECS_Msk
14684#define RNG_SR_CEIS_Pos (5U)
14685#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
14686#define RNG_SR_CEIS RNG_SR_CEIS_Msk
14687#define RNG_SR_SEIS_Pos (6U)
14688#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
14689#define RNG_SR_SEIS RNG_SR_SEIS_Msk
14690
14691/******************************************************************************/
14692/* */
14693/* Real-Time Clock (RTC) */
14694/* */
14695/******************************************************************************/
14696/*
14697 * @brief Specific device feature definitions (not present on all devices in the STM32F4 series)
14698 */
14699#define RTC_TAMPER2_SUPPORT
14700#define RTC_AF2_SUPPORT
14701/******************** Bits definition for RTC_TR register *******************/
14702#define RTC_TR_PM_Pos (22U)
14703#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
14704#define RTC_TR_PM RTC_TR_PM_Msk
14705#define RTC_TR_HT_Pos (20U)
14706#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
14707#define RTC_TR_HT RTC_TR_HT_Msk
14708#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
14709#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
14710#define RTC_TR_HU_Pos (16U)
14711#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
14712#define RTC_TR_HU RTC_TR_HU_Msk
14713#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
14714#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
14715#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
14716#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
14717#define RTC_TR_MNT_Pos (12U)
14718#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
14719#define RTC_TR_MNT RTC_TR_MNT_Msk
14720#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
14721#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
14722#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
14723#define RTC_TR_MNU_Pos (8U)
14724#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
14725#define RTC_TR_MNU RTC_TR_MNU_Msk
14726#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
14727#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
14728#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
14729#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
14730#define RTC_TR_ST_Pos (4U)
14731#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
14732#define RTC_TR_ST RTC_TR_ST_Msk
14733#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
14734#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
14735#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
14736#define RTC_TR_SU_Pos (0U)
14737#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
14738#define RTC_TR_SU RTC_TR_SU_Msk
14739#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
14740#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
14741#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
14742#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
14743
14744/******************** Bits definition for RTC_DR register *******************/
14745#define RTC_DR_YT_Pos (20U)
14746#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
14747#define RTC_DR_YT RTC_DR_YT_Msk
14748#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
14749#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
14750#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
14751#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
14752#define RTC_DR_YU_Pos (16U)
14753#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
14754#define RTC_DR_YU RTC_DR_YU_Msk
14755#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
14756#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
14757#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
14758#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
14759#define RTC_DR_WDU_Pos (13U)
14760#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
14761#define RTC_DR_WDU RTC_DR_WDU_Msk
14762#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
14763#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
14764#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
14765#define RTC_DR_MT_Pos (12U)
14766#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
14767#define RTC_DR_MT RTC_DR_MT_Msk
14768#define RTC_DR_MU_Pos (8U)
14769#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
14770#define RTC_DR_MU RTC_DR_MU_Msk
14771#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
14772#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
14773#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
14774#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
14775#define RTC_DR_DT_Pos (4U)
14776#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
14777#define RTC_DR_DT RTC_DR_DT_Msk
14778#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
14779#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
14780#define RTC_DR_DU_Pos (0U)
14781#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
14782#define RTC_DR_DU RTC_DR_DU_Msk
14783#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
14784#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
14785#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
14786#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
14787
14788/******************** Bits definition for RTC_CR register *******************/
14789#define RTC_CR_COE_Pos (23U)
14790#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
14791#define RTC_CR_COE RTC_CR_COE_Msk
14792#define RTC_CR_OSEL_Pos (21U)
14793#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
14794#define RTC_CR_OSEL RTC_CR_OSEL_Msk
14795#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
14796#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
14797#define RTC_CR_POL_Pos (20U)
14798#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
14799#define RTC_CR_POL RTC_CR_POL_Msk
14800#define RTC_CR_COSEL_Pos (19U)
14801#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
14802#define RTC_CR_COSEL RTC_CR_COSEL_Msk
14803#define RTC_CR_BKP_Pos (18U)
14804#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
14805#define RTC_CR_BKP RTC_CR_BKP_Msk
14806#define RTC_CR_SUB1H_Pos (17U)
14807#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
14808#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
14809#define RTC_CR_ADD1H_Pos (16U)
14810#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
14811#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
14812#define RTC_CR_TSIE_Pos (15U)
14813#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
14814#define RTC_CR_TSIE RTC_CR_TSIE_Msk
14815#define RTC_CR_WUTIE_Pos (14U)
14816#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
14817#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
14818#define RTC_CR_ALRBIE_Pos (13U)
14819#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
14820#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
14821#define RTC_CR_ALRAIE_Pos (12U)
14822#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
14823#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
14824#define RTC_CR_TSE_Pos (11U)
14825#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
14826#define RTC_CR_TSE RTC_CR_TSE_Msk
14827#define RTC_CR_WUTE_Pos (10U)
14828#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
14829#define RTC_CR_WUTE RTC_CR_WUTE_Msk
14830#define RTC_CR_ALRBE_Pos (9U)
14831#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
14832#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
14833#define RTC_CR_ALRAE_Pos (8U)
14834#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
14835#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
14836#define RTC_CR_DCE_Pos (7U)
14837#define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
14838#define RTC_CR_DCE RTC_CR_DCE_Msk
14839#define RTC_CR_FMT_Pos (6U)
14840#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
14841#define RTC_CR_FMT RTC_CR_FMT_Msk
14842#define RTC_CR_BYPSHAD_Pos (5U)
14843#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
14844#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
14845#define RTC_CR_REFCKON_Pos (4U)
14846#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
14847#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
14848#define RTC_CR_TSEDGE_Pos (3U)
14849#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
14850#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
14851#define RTC_CR_WUCKSEL_Pos (0U)
14852#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
14853#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
14854#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
14855#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
14856#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
14857
14858/* Legacy defines */
14859#define RTC_CR_BCK RTC_CR_BKP
14860
14861/******************** Bits definition for RTC_ISR register ******************/
14862#define RTC_ISR_RECALPF_Pos (16U)
14863#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
14864#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
14865#define RTC_ISR_TAMP1F_Pos (13U)
14866#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
14867#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
14868#define RTC_ISR_TAMP2F_Pos (14U)
14869#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
14870#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
14871#define RTC_ISR_TSOVF_Pos (12U)
14872#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
14873#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
14874#define RTC_ISR_TSF_Pos (11U)
14875#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
14876#define RTC_ISR_TSF RTC_ISR_TSF_Msk
14877#define RTC_ISR_WUTF_Pos (10U)
14878#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
14879#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
14880#define RTC_ISR_ALRBF_Pos (9U)
14881#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
14882#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
14883#define RTC_ISR_ALRAF_Pos (8U)
14884#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
14885#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
14886#define RTC_ISR_INIT_Pos (7U)
14887#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
14888#define RTC_ISR_INIT RTC_ISR_INIT_Msk
14889#define RTC_ISR_INITF_Pos (6U)
14890#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
14891#define RTC_ISR_INITF RTC_ISR_INITF_Msk
14892#define RTC_ISR_RSF_Pos (5U)
14893#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
14894#define RTC_ISR_RSF RTC_ISR_RSF_Msk
14895#define RTC_ISR_INITS_Pos (4U)
14896#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
14897#define RTC_ISR_INITS RTC_ISR_INITS_Msk
14898#define RTC_ISR_SHPF_Pos (3U)
14899#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
14900#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
14901#define RTC_ISR_WUTWF_Pos (2U)
14902#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
14903#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
14904#define RTC_ISR_ALRBWF_Pos (1U)
14905#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
14906#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
14907#define RTC_ISR_ALRAWF_Pos (0U)
14908#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
14909#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
14910
14911/******************** Bits definition for RTC_PRER register *****************/
14912#define RTC_PRER_PREDIV_A_Pos (16U)
14913#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
14914#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
14915#define RTC_PRER_PREDIV_S_Pos (0U)
14916#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
14917#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
14918
14919/******************** Bits definition for RTC_WUTR register *****************/
14920#define RTC_WUTR_WUT_Pos (0U)
14921#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
14922#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
14923
14924/******************** Bits definition for RTC_CALIBR register ***************/
14925#define RTC_CALIBR_DCS_Pos (7U)
14926#define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
14927#define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
14928#define RTC_CALIBR_DC_Pos (0U)
14929#define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
14930#define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
14931
14932/******************** Bits definition for RTC_ALRMAR register ***************/
14933#define RTC_ALRMAR_MSK4_Pos (31U)
14934#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
14935#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
14936#define RTC_ALRMAR_WDSEL_Pos (30U)
14937#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
14938#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
14939#define RTC_ALRMAR_DT_Pos (28U)
14940#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
14941#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
14942#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
14943#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
14944#define RTC_ALRMAR_DU_Pos (24U)
14945#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
14946#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
14947#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
14948#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
14949#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
14950#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
14951#define RTC_ALRMAR_MSK3_Pos (23U)
14952#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
14953#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
14954#define RTC_ALRMAR_PM_Pos (22U)
14955#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
14956#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
14957#define RTC_ALRMAR_HT_Pos (20U)
14958#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
14959#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
14960#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
14961#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
14962#define RTC_ALRMAR_HU_Pos (16U)
14963#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
14964#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
14965#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
14966#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
14967#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
14968#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
14969#define RTC_ALRMAR_MSK2_Pos (15U)
14970#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
14971#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
14972#define RTC_ALRMAR_MNT_Pos (12U)
14973#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
14974#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
14975#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
14976#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
14977#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
14978#define RTC_ALRMAR_MNU_Pos (8U)
14979#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
14980#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
14981#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
14982#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
14983#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
14984#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
14985#define RTC_ALRMAR_MSK1_Pos (7U)
14986#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
14987#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
14988#define RTC_ALRMAR_ST_Pos (4U)
14989#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
14990#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
14991#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
14992#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
14993#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
14994#define RTC_ALRMAR_SU_Pos (0U)
14995#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
14996#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
14997#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
14998#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
14999#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
15000#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
15001
15002/******************** Bits definition for RTC_ALRMBR register ***************/
15003#define RTC_ALRMBR_MSK4_Pos (31U)
15004#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
15005#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15006#define RTC_ALRMBR_WDSEL_Pos (30U)
15007#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
15008#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15009#define RTC_ALRMBR_DT_Pos (28U)
15010#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
15011#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15012#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
15013#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
15014#define RTC_ALRMBR_DU_Pos (24U)
15015#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
15016#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15017#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
15018#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
15019#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
15020#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
15021#define RTC_ALRMBR_MSK3_Pos (23U)
15022#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
15023#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15024#define RTC_ALRMBR_PM_Pos (22U)
15025#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
15026#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15027#define RTC_ALRMBR_HT_Pos (20U)
15028#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
15029#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15030#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
15031#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
15032#define RTC_ALRMBR_HU_Pos (16U)
15033#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
15034#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15035#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
15036#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
15037#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
15038#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
15039#define RTC_ALRMBR_MSK2_Pos (15U)
15040#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
15041#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15042#define RTC_ALRMBR_MNT_Pos (12U)
15043#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
15044#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15045#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
15046#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
15047#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
15048#define RTC_ALRMBR_MNU_Pos (8U)
15049#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
15050#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15051#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
15052#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
15053#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
15054#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
15055#define RTC_ALRMBR_MSK1_Pos (7U)
15056#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
15057#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15058#define RTC_ALRMBR_ST_Pos (4U)
15059#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
15060#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15061#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
15062#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
15063#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
15064#define RTC_ALRMBR_SU_Pos (0U)
15065#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
15066#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15067#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
15068#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
15069#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
15070#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
15071
15072/******************** Bits definition for RTC_WPR register ******************/
15073#define RTC_WPR_KEY_Pos (0U)
15074#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
15075#define RTC_WPR_KEY RTC_WPR_KEY_Msk
15076
15077/******************** Bits definition for RTC_SSR register ******************/
15078#define RTC_SSR_SS_Pos (0U)
15079#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
15080#define RTC_SSR_SS RTC_SSR_SS_Msk
15081
15082/******************** Bits definition for RTC_SHIFTR register ***************/
15083#define RTC_SHIFTR_SUBFS_Pos (0U)
15084#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
15085#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15086#define RTC_SHIFTR_ADD1S_Pos (31U)
15087#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
15088#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15089
15090/******************** Bits definition for RTC_TSTR register *****************/
15091#define RTC_TSTR_PM_Pos (22U)
15092#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
15093#define RTC_TSTR_PM RTC_TSTR_PM_Msk
15094#define RTC_TSTR_HT_Pos (20U)
15095#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
15096#define RTC_TSTR_HT RTC_TSTR_HT_Msk
15097#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
15098#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
15099#define RTC_TSTR_HU_Pos (16U)
15100#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
15101#define RTC_TSTR_HU RTC_TSTR_HU_Msk
15102#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
15103#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
15104#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
15105#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
15106#define RTC_TSTR_MNT_Pos (12U)
15107#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
15108#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15109#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
15110#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
15111#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
15112#define RTC_TSTR_MNU_Pos (8U)
15113#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
15114#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15115#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
15116#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
15117#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
15118#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
15119#define RTC_TSTR_ST_Pos (4U)
15120#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
15121#define RTC_TSTR_ST RTC_TSTR_ST_Msk
15122#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
15123#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
15124#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
15125#define RTC_TSTR_SU_Pos (0U)
15126#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
15127#define RTC_TSTR_SU RTC_TSTR_SU_Msk
15128#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
15129#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
15130#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
15131#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
15132
15133/******************** Bits definition for RTC_TSDR register *****************/
15134#define RTC_TSDR_WDU_Pos (13U)
15135#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
15136#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15137#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
15138#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
15139#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
15140#define RTC_TSDR_MT_Pos (12U)
15141#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
15142#define RTC_TSDR_MT RTC_TSDR_MT_Msk
15143#define RTC_TSDR_MU_Pos (8U)
15144#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
15145#define RTC_TSDR_MU RTC_TSDR_MU_Msk
15146#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
15147#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
15148#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
15149#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
15150#define RTC_TSDR_DT_Pos (4U)
15151#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
15152#define RTC_TSDR_DT RTC_TSDR_DT_Msk
15153#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
15154#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
15155#define RTC_TSDR_DU_Pos (0U)
15156#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
15157#define RTC_TSDR_DU RTC_TSDR_DU_Msk
15158#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
15159#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
15160#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
15161#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
15162
15163/******************** Bits definition for RTC_TSSSR register ****************/
15164#define RTC_TSSSR_SS_Pos (0U)
15165#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
15166#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15167
15168/******************** Bits definition for RTC_CAL register *****************/
15169#define RTC_CALR_CALP_Pos (15U)
15170#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
15171#define RTC_CALR_CALP RTC_CALR_CALP_Msk
15172#define RTC_CALR_CALW8_Pos (14U)
15173#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
15174#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15175#define RTC_CALR_CALW16_Pos (13U)
15176#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
15177#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15178#define RTC_CALR_CALM_Pos (0U)
15179#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
15180#define RTC_CALR_CALM RTC_CALR_CALM_Msk
15181#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
15182#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
15183#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
15184#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
15185#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
15186#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
15187#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
15188#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
15189#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
15190
15191/******************** Bits definition for RTC_TAFCR register ****************/
15192#define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
15193#define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
15194#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
15195#define RTC_TAFCR_TSINSEL_Pos (17U)
15196#define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
15197#define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
15198#define RTC_TAFCR_TAMP1INSEL_Pos (16U)
15199#define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
15200#define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
15201#define RTC_TAFCR_TAMPPUDIS_Pos (15U)
15202#define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
15203#define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
15204#define RTC_TAFCR_TAMPPRCH_Pos (13U)
15205#define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
15206#define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
15207#define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
15208#define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
15209#define RTC_TAFCR_TAMPFLT_Pos (11U)
15210#define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
15211#define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
15212#define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
15213#define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
15214#define RTC_TAFCR_TAMPFREQ_Pos (8U)
15215#define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
15216#define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
15217#define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
15218#define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
15219#define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
15220#define RTC_TAFCR_TAMPTS_Pos (7U)
15221#define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
15222#define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
15223#define RTC_TAFCR_TAMP2TRG_Pos (4U)
15224#define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
15225#define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
15226#define RTC_TAFCR_TAMP2E_Pos (3U)
15227#define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
15228#define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
15229#define RTC_TAFCR_TAMPIE_Pos (2U)
15230#define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
15231#define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
15232#define RTC_TAFCR_TAMP1TRG_Pos (1U)
15233#define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
15234#define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
15235#define RTC_TAFCR_TAMP1E_Pos (0U)
15236#define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
15237#define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
15238
15239/* Legacy defines */
15240#define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
15241
15242/******************** Bits definition for RTC_ALRMASSR register *************/
15243#define RTC_ALRMASSR_MASKSS_Pos (24U)
15244#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
15245#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15246#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
15247#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
15248#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
15249#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
15250#define RTC_ALRMASSR_SS_Pos (0U)
15251#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
15252#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15253
15254/******************** Bits definition for RTC_ALRMBSSR register *************/
15255#define RTC_ALRMBSSR_MASKSS_Pos (24U)
15256#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
15257#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15258#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
15259#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
15260#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
15261#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
15262#define RTC_ALRMBSSR_SS_Pos (0U)
15263#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
15264#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15265
15266/******************** Bits definition for RTC_BKP0R register ****************/
15267#define RTC_BKP0R_Pos (0U)
15268#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
15269#define RTC_BKP0R RTC_BKP0R_Msk
15270
15271/******************** Bits definition for RTC_BKP1R register ****************/
15272#define RTC_BKP1R_Pos (0U)
15273#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
15274#define RTC_BKP1R RTC_BKP1R_Msk
15275
15276/******************** Bits definition for RTC_BKP2R register ****************/
15277#define RTC_BKP2R_Pos (0U)
15278#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
15279#define RTC_BKP2R RTC_BKP2R_Msk
15280
15281/******************** Bits definition for RTC_BKP3R register ****************/
15282#define RTC_BKP3R_Pos (0U)
15283#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
15284#define RTC_BKP3R RTC_BKP3R_Msk
15285
15286/******************** Bits definition for RTC_BKP4R register ****************/
15287#define RTC_BKP4R_Pos (0U)
15288#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
15289#define RTC_BKP4R RTC_BKP4R_Msk
15290
15291/******************** Bits definition for RTC_BKP5R register ****************/
15292#define RTC_BKP5R_Pos (0U)
15293#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
15294#define RTC_BKP5R RTC_BKP5R_Msk
15295
15296/******************** Bits definition for RTC_BKP6R register ****************/
15297#define RTC_BKP6R_Pos (0U)
15298#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
15299#define RTC_BKP6R RTC_BKP6R_Msk
15300
15301/******************** Bits definition for RTC_BKP7R register ****************/
15302#define RTC_BKP7R_Pos (0U)
15303#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
15304#define RTC_BKP7R RTC_BKP7R_Msk
15305
15306/******************** Bits definition for RTC_BKP8R register ****************/
15307#define RTC_BKP8R_Pos (0U)
15308#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
15309#define RTC_BKP8R RTC_BKP8R_Msk
15310
15311/******************** Bits definition for RTC_BKP9R register ****************/
15312#define RTC_BKP9R_Pos (0U)
15313#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
15314#define RTC_BKP9R RTC_BKP9R_Msk
15315
15316/******************** Bits definition for RTC_BKP10R register ***************/
15317#define RTC_BKP10R_Pos (0U)
15318#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
15319#define RTC_BKP10R RTC_BKP10R_Msk
15320
15321/******************** Bits definition for RTC_BKP11R register ***************/
15322#define RTC_BKP11R_Pos (0U)
15323#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
15324#define RTC_BKP11R RTC_BKP11R_Msk
15325
15326/******************** Bits definition for RTC_BKP12R register ***************/
15327#define RTC_BKP12R_Pos (0U)
15328#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
15329#define RTC_BKP12R RTC_BKP12R_Msk
15330
15331/******************** Bits definition for RTC_BKP13R register ***************/
15332#define RTC_BKP13R_Pos (0U)
15333#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
15334#define RTC_BKP13R RTC_BKP13R_Msk
15335
15336/******************** Bits definition for RTC_BKP14R register ***************/
15337#define RTC_BKP14R_Pos (0U)
15338#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
15339#define RTC_BKP14R RTC_BKP14R_Msk
15340
15341/******************** Bits definition for RTC_BKP15R register ***************/
15342#define RTC_BKP15R_Pos (0U)
15343#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
15344#define RTC_BKP15R RTC_BKP15R_Msk
15345
15346/******************** Bits definition for RTC_BKP16R register ***************/
15347#define RTC_BKP16R_Pos (0U)
15348#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
15349#define RTC_BKP16R RTC_BKP16R_Msk
15350
15351/******************** Bits definition for RTC_BKP17R register ***************/
15352#define RTC_BKP17R_Pos (0U)
15353#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
15354#define RTC_BKP17R RTC_BKP17R_Msk
15355
15356/******************** Bits definition for RTC_BKP18R register ***************/
15357#define RTC_BKP18R_Pos (0U)
15358#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
15359#define RTC_BKP18R RTC_BKP18R_Msk
15360
15361/******************** Bits definition for RTC_BKP19R register ***************/
15362#define RTC_BKP19R_Pos (0U)
15363#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
15364#define RTC_BKP19R RTC_BKP19R_Msk
15365
15366/******************** Number of backup registers ******************************/
15367#define RTC_BKP_NUMBER 0x000000014U
15368
15369/******************************************************************************/
15370/* */
15371/* Serial Audio Interface */
15372/* */
15373/******************************************************************************/
15374/******************** Bit definition for SAI_GCR register *******************/
15375#define SAI_GCR_SYNCIN_Pos (0U)
15376#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
15377#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
15378#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
15379#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
15380
15381#define SAI_GCR_SYNCOUT_Pos (4U)
15382#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
15383#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
15384#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
15385#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
15386
15387/******************* Bit definition for SAI_xCR1 register *******************/
15388#define SAI_xCR1_MODE_Pos (0U)
15389#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
15390#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
15391#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
15392#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
15393
15394#define SAI_xCR1_PRTCFG_Pos (2U)
15395#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
15396#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
15397#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
15398#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
15399
15400#define SAI_xCR1_DS_Pos (5U)
15401#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
15402#define SAI_xCR1_DS SAI_xCR1_DS_Msk
15403#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
15404#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
15405#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
15406
15407#define SAI_xCR1_LSBFIRST_Pos (8U)
15408#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
15409#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
15410#define SAI_xCR1_CKSTR_Pos (9U)
15411#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
15412#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
15413
15414#define SAI_xCR1_SYNCEN_Pos (10U)
15415#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
15416#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
15417#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
15418#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
15419
15420#define SAI_xCR1_MONO_Pos (12U)
15421#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
15422#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
15423#define SAI_xCR1_OUTDRIV_Pos (13U)
15424#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
15425#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
15426#define SAI_xCR1_SAIEN_Pos (16U)
15427#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
15428#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
15429#define SAI_xCR1_DMAEN_Pos (17U)
15430#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
15431#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
15432#define SAI_xCR1_NODIV_Pos (19U)
15433#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
15434#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
15435
15436#define SAI_xCR1_MCKDIV_Pos (20U)
15437#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
15438#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
15439#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
15440#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
15441#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
15442#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
15443
15444/******************* Bit definition for SAI_xCR2 register *******************/
15445#define SAI_xCR2_FTH_Pos (0U)
15446#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
15447#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
15448#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
15449#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
15450#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
15451
15452#define SAI_xCR2_FFLUSH_Pos (3U)
15453#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
15454#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
15455#define SAI_xCR2_TRIS_Pos (4U)
15456#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
15457#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
15458#define SAI_xCR2_MUTE_Pos (5U)
15459#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
15460#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
15461#define SAI_xCR2_MUTEVAL_Pos (6U)
15462#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
15463#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
15464
15465#define SAI_xCR2_MUTECNT_Pos (7U)
15466#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
15467#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
15468#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
15469#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
15470#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
15471#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
15472#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
15473#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
15474
15475#define SAI_xCR2_CPL_Pos (13U)
15476#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
15477#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
15478
15479#define SAI_xCR2_COMP_Pos (14U)
15480#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
15481#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
15482#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
15483#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
15484
15485/****************** Bit definition for SAI_xFRCR register *******************/
15486#define SAI_xFRCR_FRL_Pos (0U)
15487#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
15488#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
15489#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
15490#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
15491#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
15492#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
15493#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
15494#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
15495#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
15496#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
15497
15498#define SAI_xFRCR_FSALL_Pos (8U)
15499#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
15500#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
15501#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
15502#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
15503#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
15504#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
15505#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
15506#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
15507#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
15508
15509#define SAI_xFRCR_FSDEF_Pos (16U)
15510#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
15511#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
15512#define SAI_xFRCR_FSPOL_Pos (17U)
15513#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
15514#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
15515#define SAI_xFRCR_FSOFF_Pos (18U)
15516#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
15517#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
15518/* Legacy defines */
15519#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15520
15521/****************** Bit definition for SAI_xSLOTR register *******************/
15522#define SAI_xSLOTR_FBOFF_Pos (0U)
15523#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
15524#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
15525#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
15526#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
15527#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
15528#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
15529#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
15530
15531#define SAI_xSLOTR_SLOTSZ_Pos (6U)
15532#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
15533#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
15534#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
15535#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
15536
15537#define SAI_xSLOTR_NBSLOT_Pos (8U)
15538#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
15539#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
15540#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
15541#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
15542#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
15543#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
15544
15545#define SAI_xSLOTR_SLOTEN_Pos (16U)
15546#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
15547#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
15548
15549/******************* Bit definition for SAI_xIMR register *******************/
15550#define SAI_xIMR_OVRUDRIE_Pos (0U)
15551#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
15552#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
15553#define SAI_xIMR_MUTEDETIE_Pos (1U)
15554#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
15555#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
15556#define SAI_xIMR_WCKCFGIE_Pos (2U)
15557#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
15558#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
15559#define SAI_xIMR_FREQIE_Pos (3U)
15560#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
15561#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
15562#define SAI_xIMR_CNRDYIE_Pos (4U)
15563#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
15564#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
15565#define SAI_xIMR_AFSDETIE_Pos (5U)
15566#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
15567#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
15568#define SAI_xIMR_LFSDETIE_Pos (6U)
15569#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
15570#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
15571
15572/******************** Bit definition for SAI_xSR register *******************/
15573#define SAI_xSR_OVRUDR_Pos (0U)
15574#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
15575#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
15576#define SAI_xSR_MUTEDET_Pos (1U)
15577#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
15578#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
15579#define SAI_xSR_WCKCFG_Pos (2U)
15580#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
15581#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
15582#define SAI_xSR_FREQ_Pos (3U)
15583#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
15584#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
15585#define SAI_xSR_CNRDY_Pos (4U)
15586#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
15587#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
15588#define SAI_xSR_AFSDET_Pos (5U)
15589#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
15590#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
15591#define SAI_xSR_LFSDET_Pos (6U)
15592#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
15593#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
15594
15595#define SAI_xSR_FLVL_Pos (16U)
15596#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
15597#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
15598#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
15599#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
15600#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
15601
15602/****************** Bit definition for SAI_xCLRFR register ******************/
15603#define SAI_xCLRFR_COVRUDR_Pos (0U)
15604#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
15605#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
15606#define SAI_xCLRFR_CMUTEDET_Pos (1U)
15607#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
15608#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
15609#define SAI_xCLRFR_CWCKCFG_Pos (2U)
15610#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
15611#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
15612#define SAI_xCLRFR_CFREQ_Pos (3U)
15613#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
15614#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
15615#define SAI_xCLRFR_CCNRDY_Pos (4U)
15616#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
15617#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
15618#define SAI_xCLRFR_CAFSDET_Pos (5U)
15619#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
15620#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
15621#define SAI_xCLRFR_CLFSDET_Pos (6U)
15622#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
15623#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
15624
15625/****************** Bit definition for SAI_xDR register ******************/
15626#define SAI_xDR_DATA_Pos (0U)
15627#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
15628#define SAI_xDR_DATA SAI_xDR_DATA_Msk
15629
15630
15631/******************************************************************************/
15632/* */
15633/* SD host Interface */
15634/* */
15635/******************************************************************************/
15636/****************** Bit definition for SDIO_POWER register ******************/
15637#define SDIO_POWER_PWRCTRL_Pos (0U)
15638#define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
15639#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
15640#define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
15641#define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
15642
15643/****************** Bit definition for SDIO_CLKCR register ******************/
15644#define SDIO_CLKCR_CLKDIV_Pos (0U)
15645#define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
15646#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
15647#define SDIO_CLKCR_CLKEN_Pos (8U)
15648#define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
15649#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
15650#define SDIO_CLKCR_PWRSAV_Pos (9U)
15651#define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
15652#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
15653#define SDIO_CLKCR_BYPASS_Pos (10U)
15654#define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
15655#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
15656
15657#define SDIO_CLKCR_WIDBUS_Pos (11U)
15658#define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
15659#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
15660#define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
15661#define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
15662
15663#define SDIO_CLKCR_NEGEDGE_Pos (13U)
15664#define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
15665#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
15666#define SDIO_CLKCR_HWFC_EN_Pos (14U)
15667#define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
15668#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
15669
15670/******************* Bit definition for SDIO_ARG register *******************/
15671#define SDIO_ARG_CMDARG_Pos (0U)
15672#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
15673#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
15674
15675/******************* Bit definition for SDIO_CMD register *******************/
15676#define SDIO_CMD_CMDINDEX_Pos (0U)
15677#define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
15678#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
15679
15680#define SDIO_CMD_WAITRESP_Pos (6U)
15681#define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
15682#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
15683#define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
15684#define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
15685
15686#define SDIO_CMD_WAITINT_Pos (8U)
15687#define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
15688#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
15689#define SDIO_CMD_WAITPEND_Pos (9U)
15690#define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
15691#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
15692#define SDIO_CMD_CPSMEN_Pos (10U)
15693#define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
15694#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
15695#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
15696#define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
15697#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
15698
15699/***************** Bit definition for SDIO_RESPCMD register *****************/
15700#define SDIO_RESPCMD_RESPCMD_Pos (0U)
15701#define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
15702#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
15703
15704/****************** Bit definition for SDIO_RESP0 register ******************/
15705#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
15706#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
15707#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
15708
15709/****************** Bit definition for SDIO_RESP1 register ******************/
15710#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
15711#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
15712#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
15713
15714/****************** Bit definition for SDIO_RESP2 register ******************/
15715#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
15716#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
15717#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
15718
15719/****************** Bit definition for SDIO_RESP3 register ******************/
15720#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
15721#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
15722#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
15723
15724/****************** Bit definition for SDIO_RESP4 register ******************/
15725#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
15726#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
15727#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
15728
15729/****************** Bit definition for SDIO_DTIMER register *****************/
15730#define SDIO_DTIMER_DATATIME_Pos (0U)
15731#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
15732#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
15733
15734/****************** Bit definition for SDIO_DLEN register *******************/
15735#define SDIO_DLEN_DATALENGTH_Pos (0U)
15736#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
15737#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
15738
15739/****************** Bit definition for SDIO_DCTRL register ******************/
15740#define SDIO_DCTRL_DTEN_Pos (0U)
15741#define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
15742#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
15743#define SDIO_DCTRL_DTDIR_Pos (1U)
15744#define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
15745#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
15746#define SDIO_DCTRL_DTMODE_Pos (2U)
15747#define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
15748#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
15749#define SDIO_DCTRL_DMAEN_Pos (3U)
15750#define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
15751#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
15752
15753#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
15754#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
15755#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
15756#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
15757#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
15758#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
15759#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
15760
15761#define SDIO_DCTRL_RWSTART_Pos (8U)
15762#define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
15763#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
15764#define SDIO_DCTRL_RWSTOP_Pos (9U)
15765#define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
15766#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
15767#define SDIO_DCTRL_RWMOD_Pos (10U)
15768#define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
15769#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
15770#define SDIO_DCTRL_SDIOEN_Pos (11U)
15771#define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
15772#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
15773
15774/****************** Bit definition for SDIO_DCOUNT register *****************/
15775#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
15776#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
15777#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
15778
15779/****************** Bit definition for SDIO_STA register ********************/
15780#define SDIO_STA_CCRCFAIL_Pos (0U)
15781#define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
15782#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
15783#define SDIO_STA_DCRCFAIL_Pos (1U)
15784#define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
15785#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
15786#define SDIO_STA_CTIMEOUT_Pos (2U)
15787#define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
15788#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
15789#define SDIO_STA_DTIMEOUT_Pos (3U)
15790#define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
15791#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
15792#define SDIO_STA_TXUNDERR_Pos (4U)
15793#define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
15794#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
15795#define SDIO_STA_RXOVERR_Pos (5U)
15796#define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
15797#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
15798#define SDIO_STA_CMDREND_Pos (6U)
15799#define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
15800#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
15801#define SDIO_STA_CMDSENT_Pos (7U)
15802#define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
15803#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
15804#define SDIO_STA_DATAEND_Pos (8U)
15805#define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
15806#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
15807#define SDIO_STA_DBCKEND_Pos (10U)
15808#define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
15809#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
15810#define SDIO_STA_CMDACT_Pos (11U)
15811#define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
15812#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
15813#define SDIO_STA_TXACT_Pos (12U)
15814#define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
15815#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
15816#define SDIO_STA_RXACT_Pos (13U)
15817#define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
15818#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
15819#define SDIO_STA_TXFIFOHE_Pos (14U)
15820#define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
15821#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
15822#define SDIO_STA_RXFIFOHF_Pos (15U)
15823#define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
15824#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
15825#define SDIO_STA_TXFIFOF_Pos (16U)
15826#define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
15827#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
15828#define SDIO_STA_RXFIFOF_Pos (17U)
15829#define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
15830#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
15831#define SDIO_STA_TXFIFOE_Pos (18U)
15832#define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
15833#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
15834#define SDIO_STA_RXFIFOE_Pos (19U)
15835#define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
15836#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
15837#define SDIO_STA_TXDAVL_Pos (20U)
15838#define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
15839#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
15840#define SDIO_STA_RXDAVL_Pos (21U)
15841#define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
15842#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
15843#define SDIO_STA_SDIOIT_Pos (22U)
15844#define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
15845#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
15846
15847/******************* Bit definition for SDIO_ICR register *******************/
15848#define SDIO_ICR_CCRCFAILC_Pos (0U)
15849#define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
15850#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
15851#define SDIO_ICR_DCRCFAILC_Pos (1U)
15852#define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
15853#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
15854#define SDIO_ICR_CTIMEOUTC_Pos (2U)
15855#define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
15856#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
15857#define SDIO_ICR_DTIMEOUTC_Pos (3U)
15858#define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
15859#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
15860#define SDIO_ICR_TXUNDERRC_Pos (4U)
15861#define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
15862#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
15863#define SDIO_ICR_RXOVERRC_Pos (5U)
15864#define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
15865#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
15866#define SDIO_ICR_CMDRENDC_Pos (6U)
15867#define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
15868#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
15869#define SDIO_ICR_CMDSENTC_Pos (7U)
15870#define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
15871#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
15872#define SDIO_ICR_DATAENDC_Pos (8U)
15873#define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
15874#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
15875#define SDIO_ICR_DBCKENDC_Pos (10U)
15876#define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
15877#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
15878#define SDIO_ICR_SDIOITC_Pos (22U)
15879#define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
15880#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
15881
15882/****************** Bit definition for SDIO_MASK register *******************/
15883#define SDIO_MASK_CCRCFAILIE_Pos (0U)
15884#define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
15885#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
15886#define SDIO_MASK_DCRCFAILIE_Pos (1U)
15887#define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
15888#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
15889#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
15890#define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
15891#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
15892#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
15893#define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
15894#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
15895#define SDIO_MASK_TXUNDERRIE_Pos (4U)
15896#define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
15897#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
15898#define SDIO_MASK_RXOVERRIE_Pos (5U)
15899#define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
15900#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
15901#define SDIO_MASK_CMDRENDIE_Pos (6U)
15902#define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
15903#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
15904#define SDIO_MASK_CMDSENTIE_Pos (7U)
15905#define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
15906#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
15907#define SDIO_MASK_DATAENDIE_Pos (8U)
15908#define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
15909#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
15910#define SDIO_MASK_DBCKENDIE_Pos (10U)
15911#define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
15912#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
15913#define SDIO_MASK_CMDACTIE_Pos (11U)
15914#define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
15915#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
15916#define SDIO_MASK_TXACTIE_Pos (12U)
15917#define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
15918#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
15919#define SDIO_MASK_RXACTIE_Pos (13U)
15920#define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
15921#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
15922#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
15923#define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
15924#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
15925#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
15926#define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
15927#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
15928#define SDIO_MASK_TXFIFOFIE_Pos (16U)
15929#define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
15930#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
15931#define SDIO_MASK_RXFIFOFIE_Pos (17U)
15932#define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
15933#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
15934#define SDIO_MASK_TXFIFOEIE_Pos (18U)
15935#define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
15936#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
15937#define SDIO_MASK_RXFIFOEIE_Pos (19U)
15938#define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
15939#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
15940#define SDIO_MASK_TXDAVLIE_Pos (20U)
15941#define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
15942#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
15943#define SDIO_MASK_RXDAVLIE_Pos (21U)
15944#define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
15945#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
15946#define SDIO_MASK_SDIOITIE_Pos (22U)
15947#define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
15948#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
15949
15950/***************** Bit definition for SDIO_FIFOCNT register *****************/
15951#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
15952#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
15953#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
15954
15955/****************** Bit definition for SDIO_FIFO register *******************/
15956#define SDIO_FIFO_FIFODATA_Pos (0U)
15957#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
15958#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
15959
15960/******************************************************************************/
15961/* */
15962/* Serial Peripheral Interface */
15963/* */
15964/******************************************************************************/
15965#define SPI_I2S_FULLDUPLEX_SUPPORT
15966
15967/******************* Bit definition for SPI_CR1 register ********************/
15968#define SPI_CR1_CPHA_Pos (0U)
15969#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
15970#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
15971#define SPI_CR1_CPOL_Pos (1U)
15972#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
15973#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
15974#define SPI_CR1_MSTR_Pos (2U)
15975#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
15976#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
15977
15978#define SPI_CR1_BR_Pos (3U)
15979#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
15980#define SPI_CR1_BR SPI_CR1_BR_Msk
15981#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
15982#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
15983#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
15984
15985#define SPI_CR1_SPE_Pos (6U)
15986#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
15987#define SPI_CR1_SPE SPI_CR1_SPE_Msk
15988#define SPI_CR1_LSBFIRST_Pos (7U)
15989#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
15990#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
15991#define SPI_CR1_SSI_Pos (8U)
15992#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
15993#define SPI_CR1_SSI SPI_CR1_SSI_Msk
15994#define SPI_CR1_SSM_Pos (9U)
15995#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
15996#define SPI_CR1_SSM SPI_CR1_SSM_Msk
15997#define SPI_CR1_RXONLY_Pos (10U)
15998#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
15999#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
16000#define SPI_CR1_DFF_Pos (11U)
16001#define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
16002#define SPI_CR1_DFF SPI_CR1_DFF_Msk
16003#define SPI_CR1_CRCNEXT_Pos (12U)
16004#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
16005#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
16006#define SPI_CR1_CRCEN_Pos (13U)
16007#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
16008#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
16009#define SPI_CR1_BIDIOE_Pos (14U)
16010#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
16011#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
16012#define SPI_CR1_BIDIMODE_Pos (15U)
16013#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
16014#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
16015
16016/******************* Bit definition for SPI_CR2 register ********************/
16017#define SPI_CR2_RXDMAEN_Pos (0U)
16018#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
16019#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
16020#define SPI_CR2_TXDMAEN_Pos (1U)
16021#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
16022#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
16023#define SPI_CR2_SSOE_Pos (2U)
16024#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
16025#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
16026#define SPI_CR2_FRF_Pos (4U)
16027#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
16028#define SPI_CR2_FRF SPI_CR2_FRF_Msk
16029#define SPI_CR2_ERRIE_Pos (5U)
16030#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
16031#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
16032#define SPI_CR2_RXNEIE_Pos (6U)
16033#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
16034#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
16035#define SPI_CR2_TXEIE_Pos (7U)
16036#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
16037#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
16038
16039/******************** Bit definition for SPI_SR register ********************/
16040#define SPI_SR_RXNE_Pos (0U)
16041#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
16042#define SPI_SR_RXNE SPI_SR_RXNE_Msk
16043#define SPI_SR_TXE_Pos (1U)
16044#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
16045#define SPI_SR_TXE SPI_SR_TXE_Msk
16046#define SPI_SR_CHSIDE_Pos (2U)
16047#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
16048#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
16049#define SPI_SR_UDR_Pos (3U)
16050#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
16051#define SPI_SR_UDR SPI_SR_UDR_Msk
16052#define SPI_SR_CRCERR_Pos (4U)
16053#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
16054#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
16055#define SPI_SR_MODF_Pos (5U)
16056#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
16057#define SPI_SR_MODF SPI_SR_MODF_Msk
16058#define SPI_SR_OVR_Pos (6U)
16059#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
16060#define SPI_SR_OVR SPI_SR_OVR_Msk
16061#define SPI_SR_BSY_Pos (7U)
16062#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
16063#define SPI_SR_BSY SPI_SR_BSY_Msk
16064#define SPI_SR_FRE_Pos (8U)
16065#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
16066#define SPI_SR_FRE SPI_SR_FRE_Msk
16067
16068/******************** Bit definition for SPI_DR register ********************/
16069#define SPI_DR_DR_Pos (0U)
16070#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
16071#define SPI_DR_DR SPI_DR_DR_Msk
16072
16073/******************* Bit definition for SPI_CRCPR register ******************/
16074#define SPI_CRCPR_CRCPOLY_Pos (0U)
16075#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
16076#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
16077
16078/****************** Bit definition for SPI_RXCRCR register ******************/
16079#define SPI_RXCRCR_RXCRC_Pos (0U)
16080#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
16081#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
16082
16083/****************** Bit definition for SPI_TXCRCR register ******************/
16084#define SPI_TXCRCR_TXCRC_Pos (0U)
16085#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
16086#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
16087
16088/****************** Bit definition for SPI_I2SCFGR register *****************/
16089#define SPI_I2SCFGR_CHLEN_Pos (0U)
16090#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
16091#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
16092
16093#define SPI_I2SCFGR_DATLEN_Pos (1U)
16094#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
16095#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
16096#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
16097#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
16098
16099#define SPI_I2SCFGR_CKPOL_Pos (3U)
16100#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
16101#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
16102
16103#define SPI_I2SCFGR_I2SSTD_Pos (4U)
16104#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
16105#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
16106#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
16107#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
16108
16109#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16110#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
16111#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
16112
16113#define SPI_I2SCFGR_I2SCFG_Pos (8U)
16114#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
16115#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
16116#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
16117#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
16118
16119#define SPI_I2SCFGR_I2SE_Pos (10U)
16120#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
16121#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
16122#define SPI_I2SCFGR_I2SMOD_Pos (11U)
16123#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
16124#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
16125#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
16126#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
16127#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
16128
16129/****************** Bit definition for SPI_I2SPR register *******************/
16130#define SPI_I2SPR_I2SDIV_Pos (0U)
16131#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
16132#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
16133#define SPI_I2SPR_ODD_Pos (8U)
16134#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
16135#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
16136#define SPI_I2SPR_MCKOE_Pos (9U)
16137#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
16138#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
16139
16140/******************************************************************************/
16141/* */
16142/* SYSCFG */
16143/* */
16144/******************************************************************************/
16145/****************** Bit definition for SYSCFG_MEMRMP register ***************/
16146#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
16147#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16148#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
16149#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16150#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16151#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
16152#define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
16153#define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_UFB_MODE_Pos)
16154#define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk
16155#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
16156#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
16157#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
16158#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
16159/* Legacy Defines */
16160#define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
16161/****************** Bit definition for SYSCFG_PMC register ******************/
16162#define SYSCFG_PMC_ADCxDC2_Pos (16U)
16163#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
16164#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
16165#define SYSCFG_PMC_ADC1DC2_Pos (16U)
16166#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
16167#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
16168#define SYSCFG_PMC_ADC2DC2_Pos (17U)
16169#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
16170#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
16171#define SYSCFG_PMC_ADC3DC2_Pos (18U)
16172#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
16173#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
16174#define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
16175#define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos)
16176#define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk
16177
16178/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16179#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16180#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
16181#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
16182#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16183#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
16184#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
16185#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16186#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
16187#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
16188#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16189#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
16190#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
16194#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
16195#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
16196#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
16197#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
16198#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
16199#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
16200#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
16201#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
16202#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
16203#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
16204#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
16205
16209#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
16210#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
16211#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
16212#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
16213#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
16214#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
16215#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
16216#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
16217#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
16218#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
16219#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
16220
16224#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
16225#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
16226#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
16227#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
16228#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
16229#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
16230#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
16231#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
16232#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
16233#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
16234#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
16235
16239#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
16240#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
16241#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
16242#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
16243#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
16244#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
16245#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
16246#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
16247#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
16248#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
16249#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
16250
16251/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
16252#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
16253#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
16254#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
16255#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
16256#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
16257#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
16258#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
16259#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
16260#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
16261#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
16262#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
16263#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
16264
16268#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
16269#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
16270#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
16271#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
16272#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
16273#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
16274#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
16275#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
16276#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
16277#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
16278#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
16279
16283#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
16284#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
16285#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
16286#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
16287#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
16288#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
16289#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
16290#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
16291#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
16292#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
16293#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
16294
16298#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
16299#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
16300#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
16301#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
16302#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
16303#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
16304#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
16305#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
16306#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
16307#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
16308#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
16309
16313#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
16314#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
16315#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
16316#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
16317#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
16318#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
16319#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
16320#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
16321#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
16322#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
16323#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
16324
16325/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
16326#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
16327#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
16328#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
16329#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
16330#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
16331#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
16332#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
16333#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
16334#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
16335#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
16336#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
16337#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
16338
16342#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
16343#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
16344#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
16345#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
16346#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
16347#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
16348#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
16349#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
16350#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
16351#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
16352
16356#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
16357#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
16358#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
16359#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
16360#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
16361#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
16362#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
16363#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
16364#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
16365#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
16366
16370#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
16371#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
16372#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
16373#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
16374#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
16375#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
16376#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
16377#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
16378#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
16379#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
16380
16384#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
16385#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
16386#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
16387#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
16388#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
16389#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
16390#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
16391#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
16392#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
16393#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
16394
16395
16396/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
16397#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
16398#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
16399#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
16400#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
16401#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
16402#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
16403#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
16404#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
16405#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
16406#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
16407#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
16408#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
16409
16413#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
16414#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
16415#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
16416#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
16417#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
16418#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
16419#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
16420#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
16421#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
16422#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
16423
16427#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
16428#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
16429#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
16430#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
16431#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
16432#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
16433#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
16434#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
16435#define SYSCFG_EXTICR4_EXTI13_PI 0x0008U
16436#define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U
16437
16441#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
16442#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
16443#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
16444#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
16445#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
16446#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
16447#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
16448#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
16449#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
16450#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
16451
16455#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
16456#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
16457#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
16458#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
16459#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
16460#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
16461#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
16462#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
16463#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
16464#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
16465
16466/****************** Bit definition for SYSCFG_CMPCR register ****************/
16467#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
16468#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
16469#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
16470#define SYSCFG_CMPCR_READY_Pos (8U)
16471#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
16472#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
16473
16474/******************************************************************************/
16475/* */
16476/* TIM */
16477/* */
16478/******************************************************************************/
16479/******************* Bit definition for TIM_CR1 register ********************/
16480#define TIM_CR1_CEN_Pos (0U)
16481#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
16482#define TIM_CR1_CEN TIM_CR1_CEN_Msk
16483#define TIM_CR1_UDIS_Pos (1U)
16484#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
16485#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
16486#define TIM_CR1_URS_Pos (2U)
16487#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
16488#define TIM_CR1_URS TIM_CR1_URS_Msk
16489#define TIM_CR1_OPM_Pos (3U)
16490#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
16491#define TIM_CR1_OPM TIM_CR1_OPM_Msk
16492#define TIM_CR1_DIR_Pos (4U)
16493#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
16494#define TIM_CR1_DIR TIM_CR1_DIR_Msk
16495
16496#define TIM_CR1_CMS_Pos (5U)
16497#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
16498#define TIM_CR1_CMS TIM_CR1_CMS_Msk
16499#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
16500#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
16501
16502#define TIM_CR1_ARPE_Pos (7U)
16503#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
16504#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
16505
16506#define TIM_CR1_CKD_Pos (8U)
16507#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
16508#define TIM_CR1_CKD TIM_CR1_CKD_Msk
16509#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
16510#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
16511
16512/******************* Bit definition for TIM_CR2 register ********************/
16513#define TIM_CR2_CCPC_Pos (0U)
16514#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
16515#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
16516#define TIM_CR2_CCUS_Pos (2U)
16517#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
16518#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
16519#define TIM_CR2_CCDS_Pos (3U)
16520#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
16521#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
16522
16523#define TIM_CR2_MMS_Pos (4U)
16524#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
16525#define TIM_CR2_MMS TIM_CR2_MMS_Msk
16526#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
16527#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
16528#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
16529
16530#define TIM_CR2_TI1S_Pos (7U)
16531#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
16532#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
16533#define TIM_CR2_OIS1_Pos (8U)
16534#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
16535#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
16536#define TIM_CR2_OIS1N_Pos (9U)
16537#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
16538#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
16539#define TIM_CR2_OIS2_Pos (10U)
16540#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
16541#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
16542#define TIM_CR2_OIS2N_Pos (11U)
16543#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
16544#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
16545#define TIM_CR2_OIS3_Pos (12U)
16546#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
16547#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
16548#define TIM_CR2_OIS3N_Pos (13U)
16549#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
16550#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
16551#define TIM_CR2_OIS4_Pos (14U)
16552#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
16553#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
16554
16555/******************* Bit definition for TIM_SMCR register *******************/
16556#define TIM_SMCR_SMS_Pos (0U)
16557#define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
16558#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
16559#define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
16560#define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
16561#define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
16562
16563#define TIM_SMCR_TS_Pos (4U)
16564#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
16565#define TIM_SMCR_TS TIM_SMCR_TS_Msk
16566#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
16567#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
16568#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
16569
16570#define TIM_SMCR_MSM_Pos (7U)
16571#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
16572#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
16573
16574#define TIM_SMCR_ETF_Pos (8U)
16575#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
16576#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
16577#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
16578#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
16579#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
16580#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
16581
16582#define TIM_SMCR_ETPS_Pos (12U)
16583#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
16584#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
16585#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
16586#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
16587
16588#define TIM_SMCR_ECE_Pos (14U)
16589#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
16590#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
16591#define TIM_SMCR_ETP_Pos (15U)
16592#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
16593#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
16594
16595/******************* Bit definition for TIM_DIER register *******************/
16596#define TIM_DIER_UIE_Pos (0U)
16597#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
16598#define TIM_DIER_UIE TIM_DIER_UIE_Msk
16599#define TIM_DIER_CC1IE_Pos (1U)
16600#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
16601#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
16602#define TIM_DIER_CC2IE_Pos (2U)
16603#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
16604#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
16605#define TIM_DIER_CC3IE_Pos (3U)
16606#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
16607#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
16608#define TIM_DIER_CC4IE_Pos (4U)
16609#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
16610#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
16611#define TIM_DIER_COMIE_Pos (5U)
16612#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
16613#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
16614#define TIM_DIER_TIE_Pos (6U)
16615#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
16616#define TIM_DIER_TIE TIM_DIER_TIE_Msk
16617#define TIM_DIER_BIE_Pos (7U)
16618#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
16619#define TIM_DIER_BIE TIM_DIER_BIE_Msk
16620#define TIM_DIER_UDE_Pos (8U)
16621#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
16622#define TIM_DIER_UDE TIM_DIER_UDE_Msk
16623#define TIM_DIER_CC1DE_Pos (9U)
16624#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
16625#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
16626#define TIM_DIER_CC2DE_Pos (10U)
16627#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
16628#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
16629#define TIM_DIER_CC3DE_Pos (11U)
16630#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
16631#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
16632#define TIM_DIER_CC4DE_Pos (12U)
16633#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
16634#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
16635#define TIM_DIER_COMDE_Pos (13U)
16636#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
16637#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
16638#define TIM_DIER_TDE_Pos (14U)
16639#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
16640#define TIM_DIER_TDE TIM_DIER_TDE_Msk
16641
16642/******************** Bit definition for TIM_SR register ********************/
16643#define TIM_SR_UIF_Pos (0U)
16644#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
16645#define TIM_SR_UIF TIM_SR_UIF_Msk
16646#define TIM_SR_CC1IF_Pos (1U)
16647#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
16648#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
16649#define TIM_SR_CC2IF_Pos (2U)
16650#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
16651#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
16652#define TIM_SR_CC3IF_Pos (3U)
16653#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
16654#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
16655#define TIM_SR_CC4IF_Pos (4U)
16656#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
16657#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
16658#define TIM_SR_COMIF_Pos (5U)
16659#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
16660#define TIM_SR_COMIF TIM_SR_COMIF_Msk
16661#define TIM_SR_TIF_Pos (6U)
16662#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
16663#define TIM_SR_TIF TIM_SR_TIF_Msk
16664#define TIM_SR_BIF_Pos (7U)
16665#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
16666#define TIM_SR_BIF TIM_SR_BIF_Msk
16667#define TIM_SR_CC1OF_Pos (9U)
16668#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
16669#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
16670#define TIM_SR_CC2OF_Pos (10U)
16671#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
16672#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
16673#define TIM_SR_CC3OF_Pos (11U)
16674#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
16675#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
16676#define TIM_SR_CC4OF_Pos (12U)
16677#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
16678#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
16679
16680/******************* Bit definition for TIM_EGR register ********************/
16681#define TIM_EGR_UG_Pos (0U)
16682#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
16683#define TIM_EGR_UG TIM_EGR_UG_Msk
16684#define TIM_EGR_CC1G_Pos (1U)
16685#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
16686#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
16687#define TIM_EGR_CC2G_Pos (2U)
16688#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
16689#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
16690#define TIM_EGR_CC3G_Pos (3U)
16691#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
16692#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
16693#define TIM_EGR_CC4G_Pos (4U)
16694#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
16695#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
16696#define TIM_EGR_COMG_Pos (5U)
16697#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
16698#define TIM_EGR_COMG TIM_EGR_COMG_Msk
16699#define TIM_EGR_TG_Pos (6U)
16700#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
16701#define TIM_EGR_TG TIM_EGR_TG_Msk
16702#define TIM_EGR_BG_Pos (7U)
16703#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
16704#define TIM_EGR_BG TIM_EGR_BG_Msk
16705
16706/****************** Bit definition for TIM_CCMR1 register *******************/
16707#define TIM_CCMR1_CC1S_Pos (0U)
16708#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
16709#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
16710#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
16711#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
16712
16713#define TIM_CCMR1_OC1FE_Pos (2U)
16714#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
16715#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
16716#define TIM_CCMR1_OC1PE_Pos (3U)
16717#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
16718#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
16719
16720#define TIM_CCMR1_OC1M_Pos (4U)
16721#define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
16722#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
16723#define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
16724#define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
16725#define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
16726
16727#define TIM_CCMR1_OC1CE_Pos (7U)
16728#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
16729#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
16730
16731#define TIM_CCMR1_CC2S_Pos (8U)
16732#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
16733#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
16734#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
16735#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
16736
16737#define TIM_CCMR1_OC2FE_Pos (10U)
16738#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
16739#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
16740#define TIM_CCMR1_OC2PE_Pos (11U)
16741#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
16742#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
16743
16744#define TIM_CCMR1_OC2M_Pos (12U)
16745#define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
16746#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
16747#define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
16748#define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
16749#define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
16750
16751#define TIM_CCMR1_OC2CE_Pos (15U)
16752#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
16753#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
16754
16755/*----------------------------------------------------------------------------*/
16756
16757#define TIM_CCMR1_IC1PSC_Pos (2U)
16758#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
16759#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
16760#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
16761#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
16762
16763#define TIM_CCMR1_IC1F_Pos (4U)
16764#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
16765#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
16766#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
16767#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
16768#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
16769#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
16770
16771#define TIM_CCMR1_IC2PSC_Pos (10U)
16772#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
16773#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
16774#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
16775#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
16776
16777#define TIM_CCMR1_IC2F_Pos (12U)
16778#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
16779#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
16780#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
16781#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
16782#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
16783#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
16784
16785/****************** Bit definition for TIM_CCMR2 register *******************/
16786#define TIM_CCMR2_CC3S_Pos (0U)
16787#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
16788#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
16789#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
16790#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
16791
16792#define TIM_CCMR2_OC3FE_Pos (2U)
16793#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
16794#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
16795#define TIM_CCMR2_OC3PE_Pos (3U)
16796#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
16797#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
16798
16799#define TIM_CCMR2_OC3M_Pos (4U)
16800#define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
16801#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
16802#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
16803#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
16804#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
16805
16806#define TIM_CCMR2_OC3CE_Pos (7U)
16807#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
16808#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
16809
16810#define TIM_CCMR2_CC4S_Pos (8U)
16811#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
16812#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
16813#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
16814#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
16815
16816#define TIM_CCMR2_OC4FE_Pos (10U)
16817#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
16818#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
16819#define TIM_CCMR2_OC4PE_Pos (11U)
16820#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
16821#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
16822
16823#define TIM_CCMR2_OC4M_Pos (12U)
16824#define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
16825#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
16826#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
16827#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
16828#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
16829
16830#define TIM_CCMR2_OC4CE_Pos (15U)
16831#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
16832#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
16833
16834/*----------------------------------------------------------------------------*/
16835
16836#define TIM_CCMR2_IC3PSC_Pos (2U)
16837#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
16838#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
16839#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
16840#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
16841
16842#define TIM_CCMR2_IC3F_Pos (4U)
16843#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
16844#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
16845#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
16846#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
16847#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
16848#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
16849
16850#define TIM_CCMR2_IC4PSC_Pos (10U)
16851#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
16852#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
16853#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
16854#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
16855
16856#define TIM_CCMR2_IC4F_Pos (12U)
16857#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
16858#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
16859#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
16860#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
16861#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
16862#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
16863
16864/******************* Bit definition for TIM_CCER register *******************/
16865#define TIM_CCER_CC1E_Pos (0U)
16866#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
16867#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
16868#define TIM_CCER_CC1P_Pos (1U)
16869#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
16870#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
16871#define TIM_CCER_CC1NE_Pos (2U)
16872#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
16873#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
16874#define TIM_CCER_CC1NP_Pos (3U)
16875#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
16876#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
16877#define TIM_CCER_CC2E_Pos (4U)
16878#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
16879#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
16880#define TIM_CCER_CC2P_Pos (5U)
16881#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
16882#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
16883#define TIM_CCER_CC2NE_Pos (6U)
16884#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
16885#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
16886#define TIM_CCER_CC2NP_Pos (7U)
16887#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
16888#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
16889#define TIM_CCER_CC3E_Pos (8U)
16890#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
16891#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
16892#define TIM_CCER_CC3P_Pos (9U)
16893#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
16894#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
16895#define TIM_CCER_CC3NE_Pos (10U)
16896#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
16897#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
16898#define TIM_CCER_CC3NP_Pos (11U)
16899#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
16900#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
16901#define TIM_CCER_CC4E_Pos (12U)
16902#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
16903#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
16904#define TIM_CCER_CC4P_Pos (13U)
16905#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
16906#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
16907#define TIM_CCER_CC4NP_Pos (15U)
16908#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
16909#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
16910
16911/******************* Bit definition for TIM_CNT register ********************/
16912#define TIM_CNT_CNT_Pos (0U)
16913#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
16914#define TIM_CNT_CNT TIM_CNT_CNT_Msk
16915
16916/******************* Bit definition for TIM_PSC register ********************/
16917#define TIM_PSC_PSC_Pos (0U)
16918#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
16919#define TIM_PSC_PSC TIM_PSC_PSC_Msk
16920
16921/******************* Bit definition for TIM_ARR register ********************/
16922#define TIM_ARR_ARR_Pos (0U)
16923#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
16924#define TIM_ARR_ARR TIM_ARR_ARR_Msk
16925
16926/******************* Bit definition for TIM_RCR register ********************/
16927#define TIM_RCR_REP_Pos (0U)
16928#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
16929#define TIM_RCR_REP TIM_RCR_REP_Msk
16930
16931/******************* Bit definition for TIM_CCR1 register *******************/
16932#define TIM_CCR1_CCR1_Pos (0U)
16933#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
16934#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
16935
16936/******************* Bit definition for TIM_CCR2 register *******************/
16937#define TIM_CCR2_CCR2_Pos (0U)
16938#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
16939#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
16940
16941/******************* Bit definition for TIM_CCR3 register *******************/
16942#define TIM_CCR3_CCR3_Pos (0U)
16943#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
16944#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
16945
16946/******************* Bit definition for TIM_CCR4 register *******************/
16947#define TIM_CCR4_CCR4_Pos (0U)
16948#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
16949#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
16950
16951/******************* Bit definition for TIM_BDTR register *******************/
16952#define TIM_BDTR_DTG_Pos (0U)
16953#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
16954#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
16955#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
16956#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
16957#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
16958#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
16959#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
16960#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
16961#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
16962#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
16963
16964#define TIM_BDTR_LOCK_Pos (8U)
16965#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
16966#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
16967#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
16968#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
16969
16970#define TIM_BDTR_OSSI_Pos (10U)
16971#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
16972#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
16973#define TIM_BDTR_OSSR_Pos (11U)
16974#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
16975#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
16976#define TIM_BDTR_BKE_Pos (12U)
16977#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
16978#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
16979#define TIM_BDTR_BKP_Pos (13U)
16980#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
16981#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
16982#define TIM_BDTR_AOE_Pos (14U)
16983#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
16984#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
16985#define TIM_BDTR_MOE_Pos (15U)
16986#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
16987#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
16988
16989/******************* Bit definition for TIM_DCR register ********************/
16990#define TIM_DCR_DBA_Pos (0U)
16991#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
16992#define TIM_DCR_DBA TIM_DCR_DBA_Msk
16993#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
16994#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
16995#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
16996#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
16997#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
16998
16999#define TIM_DCR_DBL_Pos (8U)
17000#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
17001#define TIM_DCR_DBL TIM_DCR_DBL_Msk
17002#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
17003#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
17004#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
17005#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
17006#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
17007
17008/******************* Bit definition for TIM_DMAR register *******************/
17009#define TIM_DMAR_DMAB_Pos (0U)
17010#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
17011#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
17012
17013/******************* Bit definition for TIM_OR register *********************/
17014#define TIM_OR_TI1_RMP_Pos (0U)
17015#define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
17016#define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
17017#define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
17018#define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
17019
17020#define TIM_OR_TI4_RMP_Pos (6U)
17021#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
17022#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
17023#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
17024#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
17025#define TIM_OR_ITR1_RMP_Pos (10U)
17026#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
17027#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
17028#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
17029#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
17030
17031
17032/******************************************************************************/
17033/* */
17034/* Universal Synchronous Asynchronous Receiver Transmitter */
17035/* */
17036/******************************************************************************/
17037/******************* Bit definition for USART_SR register *******************/
17038#define USART_SR_PE_Pos (0U)
17039#define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
17040#define USART_SR_PE USART_SR_PE_Msk
17041#define USART_SR_FE_Pos (1U)
17042#define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
17043#define USART_SR_FE USART_SR_FE_Msk
17044#define USART_SR_NE_Pos (2U)
17045#define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
17046#define USART_SR_NE USART_SR_NE_Msk
17047#define USART_SR_ORE_Pos (3U)
17048#define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
17049#define USART_SR_ORE USART_SR_ORE_Msk
17050#define USART_SR_IDLE_Pos (4U)
17051#define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
17052#define USART_SR_IDLE USART_SR_IDLE_Msk
17053#define USART_SR_RXNE_Pos (5U)
17054#define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
17055#define USART_SR_RXNE USART_SR_RXNE_Msk
17056#define USART_SR_TC_Pos (6U)
17057#define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
17058#define USART_SR_TC USART_SR_TC_Msk
17059#define USART_SR_TXE_Pos (7U)
17060#define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
17061#define USART_SR_TXE USART_SR_TXE_Msk
17062#define USART_SR_LBD_Pos (8U)
17063#define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
17064#define USART_SR_LBD USART_SR_LBD_Msk
17065#define USART_SR_CTS_Pos (9U)
17066#define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
17067#define USART_SR_CTS USART_SR_CTS_Msk
17068
17069/******************* Bit definition for USART_DR register *******************/
17070#define USART_DR_DR_Pos (0U)
17071#define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
17072#define USART_DR_DR USART_DR_DR_Msk
17073
17074/****************** Bit definition for USART_BRR register *******************/
17075#define USART_BRR_DIV_Fraction_Pos (0U)
17076#define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
17077#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
17078#define USART_BRR_DIV_Mantissa_Pos (4U)
17079#define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
17080#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
17081
17082/****************** Bit definition for USART_CR1 register *******************/
17083#define USART_CR1_SBK_Pos (0U)
17084#define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
17085#define USART_CR1_SBK USART_CR1_SBK_Msk
17086#define USART_CR1_RWU_Pos (1U)
17087#define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
17088#define USART_CR1_RWU USART_CR1_RWU_Msk
17089#define USART_CR1_RE_Pos (2U)
17090#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
17091#define USART_CR1_RE USART_CR1_RE_Msk
17092#define USART_CR1_TE_Pos (3U)
17093#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
17094#define USART_CR1_TE USART_CR1_TE_Msk
17095#define USART_CR1_IDLEIE_Pos (4U)
17096#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
17097#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
17098#define USART_CR1_RXNEIE_Pos (5U)
17099#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
17100#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
17101#define USART_CR1_TCIE_Pos (6U)
17102#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
17103#define USART_CR1_TCIE USART_CR1_TCIE_Msk
17104#define USART_CR1_TXEIE_Pos (7U)
17105#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
17106#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
17107#define USART_CR1_PEIE_Pos (8U)
17108#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
17109#define USART_CR1_PEIE USART_CR1_PEIE_Msk
17110#define USART_CR1_PS_Pos (9U)
17111#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
17112#define USART_CR1_PS USART_CR1_PS_Msk
17113#define USART_CR1_PCE_Pos (10U)
17114#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
17115#define USART_CR1_PCE USART_CR1_PCE_Msk
17116#define USART_CR1_WAKE_Pos (11U)
17117#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
17118#define USART_CR1_WAKE USART_CR1_WAKE_Msk
17119#define USART_CR1_M_Pos (12U)
17120#define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
17121#define USART_CR1_M USART_CR1_M_Msk
17122#define USART_CR1_UE_Pos (13U)
17123#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
17124#define USART_CR1_UE USART_CR1_UE_Msk
17125#define USART_CR1_OVER8_Pos (15U)
17126#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
17127#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
17128
17129/****************** Bit definition for USART_CR2 register *******************/
17130#define USART_CR2_ADD_Pos (0U)
17131#define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
17132#define USART_CR2_ADD USART_CR2_ADD_Msk
17133#define USART_CR2_LBDL_Pos (5U)
17134#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
17135#define USART_CR2_LBDL USART_CR2_LBDL_Msk
17136#define USART_CR2_LBDIE_Pos (6U)
17137#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
17138#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
17139#define USART_CR2_LBCL_Pos (8U)
17140#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
17141#define USART_CR2_LBCL USART_CR2_LBCL_Msk
17142#define USART_CR2_CPHA_Pos (9U)
17143#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
17144#define USART_CR2_CPHA USART_CR2_CPHA_Msk
17145#define USART_CR2_CPOL_Pos (10U)
17146#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
17147#define USART_CR2_CPOL USART_CR2_CPOL_Msk
17148#define USART_CR2_CLKEN_Pos (11U)
17149#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
17150#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
17151
17152#define USART_CR2_STOP_Pos (12U)
17153#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
17154#define USART_CR2_STOP USART_CR2_STOP_Msk
17155#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
17156#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
17157
17158#define USART_CR2_LINEN_Pos (14U)
17159#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
17160#define USART_CR2_LINEN USART_CR2_LINEN_Msk
17161
17162/****************** Bit definition for USART_CR3 register *******************/
17163#define USART_CR3_EIE_Pos (0U)
17164#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
17165#define USART_CR3_EIE USART_CR3_EIE_Msk
17166#define USART_CR3_IREN_Pos (1U)
17167#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
17168#define USART_CR3_IREN USART_CR3_IREN_Msk
17169#define USART_CR3_IRLP_Pos (2U)
17170#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
17171#define USART_CR3_IRLP USART_CR3_IRLP_Msk
17172#define USART_CR3_HDSEL_Pos (3U)
17173#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
17174#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
17175#define USART_CR3_NACK_Pos (4U)
17176#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
17177#define USART_CR3_NACK USART_CR3_NACK_Msk
17178#define USART_CR3_SCEN_Pos (5U)
17179#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
17180#define USART_CR3_SCEN USART_CR3_SCEN_Msk
17181#define USART_CR3_DMAR_Pos (6U)
17182#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
17183#define USART_CR3_DMAR USART_CR3_DMAR_Msk
17184#define USART_CR3_DMAT_Pos (7U)
17185#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
17186#define USART_CR3_DMAT USART_CR3_DMAT_Msk
17187#define USART_CR3_RTSE_Pos (8U)
17188#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
17189#define USART_CR3_RTSE USART_CR3_RTSE_Msk
17190#define USART_CR3_CTSE_Pos (9U)
17191#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
17192#define USART_CR3_CTSE USART_CR3_CTSE_Msk
17193#define USART_CR3_CTSIE_Pos (10U)
17194#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
17195#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
17196#define USART_CR3_ONEBIT_Pos (11U)
17197#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
17198#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
17199
17200/****************** Bit definition for USART_GTPR register ******************/
17201#define USART_GTPR_PSC_Pos (0U)
17202#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
17203#define USART_GTPR_PSC USART_GTPR_PSC_Msk
17204#define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
17205#define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
17206#define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
17207#define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
17208#define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
17209#define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
17210#define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
17211#define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
17212
17213#define USART_GTPR_GT_Pos (8U)
17214#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
17215#define USART_GTPR_GT USART_GTPR_GT_Msk
17216
17217/******************************************************************************/
17218/* */
17219/* Window WATCHDOG */
17220/* */
17221/******************************************************************************/
17222/******************* Bit definition for WWDG_CR register ********************/
17223#define WWDG_CR_T_Pos (0U)
17224#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
17225#define WWDG_CR_T WWDG_CR_T_Msk
17226#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
17227#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
17228#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
17229#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
17230#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
17231#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
17232#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
17233/* Legacy defines */
17234#define WWDG_CR_T0 WWDG_CR_T_0
17235#define WWDG_CR_T1 WWDG_CR_T_1
17236#define WWDG_CR_T2 WWDG_CR_T_2
17237#define WWDG_CR_T3 WWDG_CR_T_3
17238#define WWDG_CR_T4 WWDG_CR_T_4
17239#define WWDG_CR_T5 WWDG_CR_T_5
17240#define WWDG_CR_T6 WWDG_CR_T_6
17241
17242#define WWDG_CR_WDGA_Pos (7U)
17243#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
17244#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
17245
17246/******************* Bit definition for WWDG_CFR register *******************/
17247#define WWDG_CFR_W_Pos (0U)
17248#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
17249#define WWDG_CFR_W WWDG_CFR_W_Msk
17250#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
17251#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
17252#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
17253#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
17254#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
17255#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
17256#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
17257/* Legacy defines */
17258#define WWDG_CFR_W0 WWDG_CFR_W_0
17259#define WWDG_CFR_W1 WWDG_CFR_W_1
17260#define WWDG_CFR_W2 WWDG_CFR_W_2
17261#define WWDG_CFR_W3 WWDG_CFR_W_3
17262#define WWDG_CFR_W4 WWDG_CFR_W_4
17263#define WWDG_CFR_W5 WWDG_CFR_W_5
17264#define WWDG_CFR_W6 WWDG_CFR_W_6
17265
17266#define WWDG_CFR_WDGTB_Pos (7U)
17267#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
17268#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
17269#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
17270#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
17271/* Legacy defines */
17272#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
17273#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
17274
17275#define WWDG_CFR_EWI_Pos (9U)
17276#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
17277#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
17278
17279/******************* Bit definition for WWDG_SR register ********************/
17280#define WWDG_SR_EWIF_Pos (0U)
17281#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
17282#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
17283
17284
17285/******************************************************************************/
17286/* */
17287/* DBG */
17288/* */
17289/******************************************************************************/
17290/******************** Bit definition for DBGMCU_IDCODE register *************/
17291#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
17292#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
17293#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
17294#define DBGMCU_IDCODE_REV_ID_Pos (16U)
17295#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
17296#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
17297
17298/******************** Bit definition for DBGMCU_CR register *****************/
17299#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
17300#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
17301#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
17302#define DBGMCU_CR_DBG_STOP_Pos (1U)
17303#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
17304#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
17305#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
17306#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
17307#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
17308#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
17309#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
17310#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
17311
17312#define DBGMCU_CR_TRACE_MODE_Pos (6U)
17313#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
17314#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
17315#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
17316#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
17317
17318/******************** Bit definition for DBGMCU_APB1_FZ register ************/
17319#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
17320#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
17321#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17322#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
17323#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
17324#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17325#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
17326#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
17327#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17328#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
17329#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
17330#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17331#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
17332#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
17333#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17334#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
17335#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
17336#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17337#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
17338#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
17339#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17340#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
17341#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
17342#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17343#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
17344#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
17345#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17346#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
17347#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
17348#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17349#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
17350#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
17351#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17352#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
17353#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
17354#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17355#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
17356#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
17357#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17358#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
17359#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
17360#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17361#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
17362#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
17363#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17364#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
17365#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos)
17366#define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17367#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
17368#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
17369#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17370#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
17371#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos)
17372#define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17373/* Old IWDGSTOP bit definition, maintained for legacy purpose */
17374#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
17375
17376/******************** Bit definition for DBGMCU_APB2_FZ register ************/
17377#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
17378#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
17379#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17380#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
17381#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
17382#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17383#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
17384#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
17385#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17386#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
17387#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
17388#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17389#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
17390#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
17391#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17392
17393/******************************************************************************/
17394/* */
17395/* Ethernet MAC Registers bits definitions */
17396/* */
17397/******************************************************************************/
17398/* Bit definition for Ethernet MAC Control Register register */
17399#define ETH_MACCR_CSTF_Pos (25U)
17400#define ETH_MACCR_CSTF_Msk (0x1UL << ETH_MACCR_CSTF_Pos)
17401#define ETH_MACCR_CSTF ETH_MACCR_CSTF_Msk /* CRC stripping for Type frames */
17402#define ETH_MACCR_WD_Pos (23U)
17403#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
17404#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
17405#define ETH_MACCR_JD_Pos (22U)
17406#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
17407#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
17408#define ETH_MACCR_IFG_Pos (17U)
17409#define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)
17410#define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
17411#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
17412#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
17413#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
17414#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
17415#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
17416#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
17417#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
17418#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
17419#define ETH_MACCR_CSD_Pos (16U)
17420#define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)
17421#define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
17422#define ETH_MACCR_FES_Pos (14U)
17423#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
17424#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
17425#define ETH_MACCR_ROD_Pos (13U)
17426#define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)
17427#define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
17428#define ETH_MACCR_LM_Pos (12U)
17429#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
17430#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
17431#define ETH_MACCR_DM_Pos (11U)
17432#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
17433#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
17434#define ETH_MACCR_IPCO_Pos (10U)
17435#define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)
17436#define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
17437#define ETH_MACCR_RD_Pos (9U)
17438#define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)
17439#define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
17440#define ETH_MACCR_APCS_Pos (7U)
17441#define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)
17442#define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
17443#define ETH_MACCR_BL_Pos (5U)
17444#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
17445#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17446 a transmission attempt during retries after a collision: 0 =< r <2^k */
17447#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
17448#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
17449#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
17450#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
17451#define ETH_MACCR_DC_Pos (4U)
17452#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
17453#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
17454#define ETH_MACCR_TE_Pos (3U)
17455#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
17456#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
17457#define ETH_MACCR_RE_Pos (2U)
17458#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
17459#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
17460
17461/* Bit definition for Ethernet MAC Frame Filter Register */
17462#define ETH_MACFFR_RA_Pos (31U)
17463#define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)
17464#define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
17465#define ETH_MACFFR_HPF_Pos (10U)
17466#define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)
17467#define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
17468#define ETH_MACFFR_SAF_Pos (9U)
17469#define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)
17470#define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
17471#define ETH_MACFFR_SAIF_Pos (8U)
17472#define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)
17473#define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
17474#define ETH_MACFFR_PCF_Pos (6U)
17475#define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)
17476#define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
17477#define ETH_MACFFR_PCF_BlockAll_Pos (6U)
17478#define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)
17479#define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17480#define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
17481#define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)
17482#define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17483#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
17484#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)
17485#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17486#define ETH_MACFFR_BFD_Pos (5U)
17487#define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)
17488#define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
17489#define ETH_MACFFR_PAM_Pos (4U)
17490#define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)
17491#define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
17492#define ETH_MACFFR_DAIF_Pos (3U)
17493#define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)
17494#define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
17495#define ETH_MACFFR_HM_Pos (2U)
17496#define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)
17497#define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
17498#define ETH_MACFFR_HU_Pos (1U)
17499#define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)
17500#define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
17501#define ETH_MACFFR_PM_Pos (0U)
17502#define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)
17503#define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
17504
17505/* Bit definition for Ethernet MAC Hash Table High Register */
17506#define ETH_MACHTHR_HTH_Pos (0U)
17507#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
17508#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
17509
17510/* Bit definition for Ethernet MAC Hash Table Low Register */
17511#define ETH_MACHTLR_HTL_Pos (0U)
17512#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
17513#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
17514
17515/* Bit definition for Ethernet MAC MII Address Register */
17516#define ETH_MACMIIAR_PA_Pos (11U)
17517#define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)
17518#define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
17519#define ETH_MACMIIAR_MR_Pos (6U)
17520#define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)
17521#define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
17522#define ETH_MACMIIAR_CR_Pos (2U)
17523#define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)
17524#define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
17525#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
17526#define ETH_MACMIIAR_CR_Div62_Pos (2U)
17527#define ETH_MACMIIAR_CR_Div62_Msk (0x1UL << ETH_MACMIIAR_CR_Div62_Pos)
17528#define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
17529#define ETH_MACMIIAR_CR_Div16_Pos (3U)
17530#define ETH_MACMIIAR_CR_Div16_Msk (0x1UL << ETH_MACMIIAR_CR_Div16_Pos)
17531#define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
17532#define ETH_MACMIIAR_CR_Div26_Pos (2U)
17533#define ETH_MACMIIAR_CR_Div26_Msk (0x3UL << ETH_MACMIIAR_CR_Div26_Pos)
17534#define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
17535#define ETH_MACMIIAR_CR_Div102_Pos (4U)
17536#define ETH_MACMIIAR_CR_Div102_Msk (0x1UL << ETH_MACMIIAR_CR_Div102_Pos)
17537#define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17538#define ETH_MACMIIAR_MW_Pos (1U)
17539#define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)
17540#define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
17541#define ETH_MACMIIAR_MB_Pos (0U)
17542#define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)
17543#define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
17544
17545/* Bit definition for Ethernet MAC MII Data Register */
17546#define ETH_MACMIIDR_MD_Pos (0U)
17547#define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)
17548#define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
17549
17550/* Bit definition for Ethernet MAC Flow Control Register */
17551#define ETH_MACFCR_PT_Pos (16U)
17552#define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)
17553#define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
17554#define ETH_MACFCR_ZQPD_Pos (7U)
17555#define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)
17556#define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
17557#define ETH_MACFCR_PLT_Pos (4U)
17558#define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)
17559#define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
17560#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
17561#define ETH_MACFCR_PLT_Minus28_Pos (4U)
17562#define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)
17563#define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
17564#define ETH_MACFCR_PLT_Minus144_Pos (5U)
17565#define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)
17566#define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17567#define ETH_MACFCR_PLT_Minus256_Pos (4U)
17568#define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)
17569#define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17570#define ETH_MACFCR_UPFD_Pos (3U)
17571#define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)
17572#define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
17573#define ETH_MACFCR_RFCE_Pos (2U)
17574#define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)
17575#define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
17576#define ETH_MACFCR_TFCE_Pos (1U)
17577#define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)
17578#define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
17579#define ETH_MACFCR_FCBBPA_Pos (0U)
17580#define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)
17581#define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
17582
17583/* Bit definition for Ethernet MAC VLAN Tag Register */
17584#define ETH_MACVLANTR_VLANTC_Pos (16U)
17585#define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)
17586#define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17587#define ETH_MACVLANTR_VLANTI_Pos (0U)
17588#define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)
17589#define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17590
17591/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17592#define ETH_MACRWUFFR_D_Pos (0U)
17593#define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)
17594#define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
17595/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17596 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17597/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17598 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17599 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17600 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17601 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17602 RSVD - Filter1 Command - RSVD - Filter0 Command
17603 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17604 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17605 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17606
17607/* Bit definition for Ethernet MAC PMT Control and Status Register */
17608#define ETH_MACPMTCSR_WFFRPR_Pos (31U)
17609#define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)
17610#define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17611#define ETH_MACPMTCSR_GU_Pos (9U)
17612#define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)
17613#define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
17614#define ETH_MACPMTCSR_WFR_Pos (6U)
17615#define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)
17616#define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
17617#define ETH_MACPMTCSR_MPR_Pos (5U)
17618#define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)
17619#define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
17620#define ETH_MACPMTCSR_WFE_Pos (2U)
17621#define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)
17622#define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
17623#define ETH_MACPMTCSR_MPE_Pos (1U)
17624#define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)
17625#define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
17626#define ETH_MACPMTCSR_PD_Pos (0U)
17627#define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)
17628#define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
17629
17630/* Bit definition for Ethernet MAC debug Register */
17631#define ETH_MACDBGR_TFF_Pos (25U)
17632#define ETH_MACDBGR_TFF_Msk (0x1UL << ETH_MACDBGR_TFF_Pos)
17633#define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
17634#define ETH_MACDBGR_TFNE_Pos (24U)
17635#define ETH_MACDBGR_TFNE_Msk (0x1UL << ETH_MACDBGR_TFNE_Pos)
17636#define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
17637#define ETH_MACDBGR_TFWA_Pos (22U)
17638#define ETH_MACDBGR_TFWA_Msk (0x1UL << ETH_MACDBGR_TFWA_Pos)
17639#define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
17640#define ETH_MACDBGR_TFRS_Pos (20U)
17641#define ETH_MACDBGR_TFRS_Msk (0x3UL << ETH_MACDBGR_TFRS_Pos)
17642#define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
17643#define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
17644#define ETH_MACDBGR_TFRS_WRITING_Msk (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos)
17645#define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
17646#define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
17647#define ETH_MACDBGR_TFRS_WAITING_Msk (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos)
17648#define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
17649#define ETH_MACDBGR_TFRS_READ_Pos (20U)
17650#define ETH_MACDBGR_TFRS_READ_Msk (0x1UL << ETH_MACDBGR_TFRS_READ_Pos)
17651#define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
17652#define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
17653#define ETH_MACDBGR_MTP_Pos (19U)
17654#define ETH_MACDBGR_MTP_Msk (0x1UL << ETH_MACDBGR_MTP_Pos)
17655#define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
17656#define ETH_MACDBGR_MTFCS_Pos (17U)
17657#define ETH_MACDBGR_MTFCS_Msk (0x3UL << ETH_MACDBGR_MTFCS_Pos)
17658#define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
17659#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
17660#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos)
17661#define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
17662#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
17663#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos)
17664#define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17665#define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
17666#define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos)
17667#define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
17668#define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
17669#define ETH_MACDBGR_MMTEA_Pos (16U)
17670#define ETH_MACDBGR_MMTEA_Msk (0x1UL << ETH_MACDBGR_MMTEA_Pos)
17671#define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
17672#define ETH_MACDBGR_RFFL_Pos (8U)
17673#define ETH_MACDBGR_RFFL_Msk (0x3UL << ETH_MACDBGR_RFFL_Pos)
17674#define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
17675#define ETH_MACDBGR_RFFL_FULL_Pos (8U)
17676#define ETH_MACDBGR_RFFL_FULL_Msk (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos)
17677#define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
17678#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
17679#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos)
17680#define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
17681#define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
17682#define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos)
17683#define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
17684#define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
17685#define ETH_MACDBGR_RFRCS_Pos (5U)
17686#define ETH_MACDBGR_RFRCS_Msk (0x3UL << ETH_MACDBGR_RFRCS_Pos)
17687#define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
17688#define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
17689#define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos)
17690#define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
17691#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
17692#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos)
17693#define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
17694#define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
17695#define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos)
17696#define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
17697#define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
17698#define ETH_MACDBGR_RFWRA_Pos (4U)
17699#define ETH_MACDBGR_RFWRA_Msk (0x1UL << ETH_MACDBGR_RFWRA_Pos)
17700#define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
17701#define ETH_MACDBGR_MSFRWCS_Pos (1U)
17702#define ETH_MACDBGR_MSFRWCS_Msk (0x3UL << ETH_MACDBGR_MSFRWCS_Pos)
17703#define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
17704#define ETH_MACDBGR_MSFRWCS_1 (0x2UL << ETH_MACDBGR_MSFRWCS_Pos)
17705#define ETH_MACDBGR_MSFRWCS_0 (0x1UL << ETH_MACDBGR_MSFRWCS_Pos)
17706#define ETH_MACDBGR_MMRPEA_Pos (0U)
17707#define ETH_MACDBGR_MMRPEA_Msk (0x1UL << ETH_MACDBGR_MMRPEA_Pos)
17708#define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
17709
17710/* Bit definition for Ethernet MAC Status Register */
17711#define ETH_MACSR_TSTS_Pos (9U)
17712#define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)
17713#define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
17714#define ETH_MACSR_MMCTS_Pos (6U)
17715#define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)
17716#define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
17717#define ETH_MACSR_MMMCRS_Pos (5U)
17718#define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)
17719#define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
17720#define ETH_MACSR_MMCS_Pos (4U)
17721#define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)
17722#define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
17723#define ETH_MACSR_PMTS_Pos (3U)
17724#define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)
17725#define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
17726
17727/* Bit definition for Ethernet MAC Interrupt Mask Register */
17728#define ETH_MACIMR_TSTIM_Pos (9U)
17729#define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)
17730#define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
17731#define ETH_MACIMR_PMTIM_Pos (3U)
17732#define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)
17733#define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
17734
17735/* Bit definition for Ethernet MAC Address0 High Register */
17736#define ETH_MACA0HR_MACA0H_Pos (0U)
17737#define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)
17738#define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
17739
17740/* Bit definition for Ethernet MAC Address0 Low Register */
17741#define ETH_MACA0LR_MACA0L_Pos (0U)
17742#define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)
17743#define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
17744
17745/* Bit definition for Ethernet MAC Address1 High Register */
17746#define ETH_MACA1HR_AE_Pos (31U)
17747#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
17748#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
17749#define ETH_MACA1HR_SA_Pos (30U)
17750#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
17751#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
17752#define ETH_MACA1HR_MBC_Pos (24U)
17753#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
17754#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
17755#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17756#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17757#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17758#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17759#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17760#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
17761#define ETH_MACA1HR_MACA1H_Pos (0U)
17762#define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)
17763#define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
17764
17765/* Bit definition for Ethernet MAC Address1 Low Register */
17766#define ETH_MACA1LR_MACA1L_Pos (0U)
17767#define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)
17768#define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
17769
17770/* Bit definition for Ethernet MAC Address2 High Register */
17771#define ETH_MACA2HR_AE_Pos (31U)
17772#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
17773#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
17774#define ETH_MACA2HR_SA_Pos (30U)
17775#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
17776#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
17777#define ETH_MACA2HR_MBC_Pos (24U)
17778#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
17779#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
17780#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17781#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17782#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17783#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17784#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17785#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
17786#define ETH_MACA2HR_MACA2H_Pos (0U)
17787#define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)
17788#define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
17789
17790/* Bit definition for Ethernet MAC Address2 Low Register */
17791#define ETH_MACA2LR_MACA2L_Pos (0U)
17792#define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)
17793#define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
17794
17795/* Bit definition for Ethernet MAC Address3 High Register */
17796#define ETH_MACA3HR_AE_Pos (31U)
17797#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
17798#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
17799#define ETH_MACA3HR_SA_Pos (30U)
17800#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
17801#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
17802#define ETH_MACA3HR_MBC_Pos (24U)
17803#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
17804#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
17805#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17806#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17807#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17808#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17809#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17810#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
17811#define ETH_MACA3HR_MACA3H_Pos (0U)
17812#define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)
17813#define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
17814
17815/* Bit definition for Ethernet MAC Address3 Low Register */
17816#define ETH_MACA3LR_MACA3L_Pos (0U)
17817#define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)
17818#define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
17819
17820/******************************************************************************/
17821/* Ethernet MMC Registers bits definition */
17822/******************************************************************************/
17823
17824/* Bit definition for Ethernet MMC Control Register */
17825#define ETH_MMCCR_MCFHP_Pos (5U)
17826#define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos)
17827#define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
17828#define ETH_MMCCR_MCP_Pos (4U)
17829#define ETH_MMCCR_MCP_Msk (0x1UL << ETH_MMCCR_MCP_Pos)
17830#define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
17831#define ETH_MMCCR_MCF_Pos (3U)
17832#define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)
17833#define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
17834#define ETH_MMCCR_ROR_Pos (2U)
17835#define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)
17836#define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
17837#define ETH_MMCCR_CSR_Pos (1U)
17838#define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)
17839#define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
17840#define ETH_MMCCR_CR_Pos (0U)
17841#define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)
17842#define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
17843
17844/* Bit definition for Ethernet MMC Receive Interrupt Register */
17845#define ETH_MMCRIR_RGUFS_Pos (17U)
17846#define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)
17847#define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
17848#define ETH_MMCRIR_RFAES_Pos (6U)
17849#define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)
17850#define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
17851#define ETH_MMCRIR_RFCES_Pos (5U)
17852#define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)
17853#define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
17854
17855/* Bit definition for Ethernet MMC Transmit Interrupt Register */
17856#define ETH_MMCTIR_TGFS_Pos (21U)
17857#define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)
17858#define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
17859#define ETH_MMCTIR_TGFMSCS_Pos (15U)
17860#define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)
17861#define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
17862#define ETH_MMCTIR_TGFSCS_Pos (14U)
17863#define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)
17864#define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
17865
17866/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
17867#define ETH_MMCRIMR_RGUFM_Pos (17U)
17868#define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)
17869#define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
17870#define ETH_MMCRIMR_RFAEM_Pos (6U)
17871#define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)
17872#define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
17873#define ETH_MMCRIMR_RFCEM_Pos (5U)
17874#define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)
17875#define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
17876
17877/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
17878#define ETH_MMCTIMR_TGFM_Pos (21U)
17879#define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)
17880#define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
17881#define ETH_MMCTIMR_TGFMSCM_Pos (15U)
17882#define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)
17883#define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
17884#define ETH_MMCTIMR_TGFSCM_Pos (14U)
17885#define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)
17886#define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
17887
17888/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
17889#define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
17890#define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)
17891#define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
17892
17893/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
17894#define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
17895#define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)
17896#define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
17897
17898/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
17899#define ETH_MMCTGFCR_TGFC_Pos (0U)
17900#define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)
17901#define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
17902
17903/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
17904#define ETH_MMCRFCECR_RFCEC_Pos (0U)
17905#define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)
17906#define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
17907
17908/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
17909#define ETH_MMCRFAECR_RFAEC_Pos (0U)
17910#define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)
17911#define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
17912
17913/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
17914#define ETH_MMCRGUFCR_RGUFC_Pos (0U)
17915#define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)
17916#define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
17917
17918/******************************************************************************/
17919/* Ethernet PTP Registers bits definition */
17920/******************************************************************************/
17921
17922/* Bit definition for Ethernet PTP Time Stamp Control Register */
17923#define ETH_PTPTSCR_TSPFFMAE_Pos (18U)
17924#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos)
17925#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */
17926#define ETH_PTPTSCR_TSCNT_Pos (16U)
17927#define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos)
17928#define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
17929#define ETH_PTPTSCR_TSSMRME_Pos (15U)
17930#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos)
17931#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
17932#define ETH_PTPTSCR_TSSEME_Pos (14U)
17933#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos)
17934#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */
17935#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U)
17936#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos)
17937#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
17938#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U)
17939#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos)
17940#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
17941#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U)
17942#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos)
17943#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
17944#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U)
17945#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos)
17946#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
17947#define ETH_PTPTSCR_TSSSR_Pos (9U)
17948#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos)
17949#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
17950#define ETH_PTPTSCR_TSSARFE_Pos (8U)
17951#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos)
17952#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
17954#define ETH_PTPTSCR_TSARU_Pos (5U)
17955#define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)
17956#define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
17957#define ETH_PTPTSCR_TSITE_Pos (4U)
17958#define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)
17959#define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
17960#define ETH_PTPTSCR_TSSTU_Pos (3U)
17961#define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)
17962#define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
17963#define ETH_PTPTSCR_TSSTI_Pos (2U)
17964#define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)
17965#define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
17966#define ETH_PTPTSCR_TSFCU_Pos (1U)
17967#define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)
17968#define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
17969#define ETH_PTPTSCR_TSE_Pos (0U)
17970#define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)
17971#define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
17972
17973/* Bit definition for Ethernet PTP Sub-Second Increment Register */
17974#define ETH_PTPSSIR_STSSI_Pos (0U)
17975#define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)
17976#define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
17977
17978/* Bit definition for Ethernet PTP Time Stamp High Register */
17979#define ETH_PTPTSHR_STS_Pos (0U)
17980#define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)
17981#define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
17982
17983/* Bit definition for Ethernet PTP Time Stamp Low Register */
17984#define ETH_PTPTSLR_STPNS_Pos (31U)
17985#define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)
17986#define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
17987#define ETH_PTPTSLR_STSS_Pos (0U)
17988#define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)
17989#define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
17990
17991/* Bit definition for Ethernet PTP Time Stamp High Update Register */
17992#define ETH_PTPTSHUR_TSUS_Pos (0U)
17993#define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)
17994#define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
17995
17996/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
17997#define ETH_PTPTSLUR_TSUPNS_Pos (31U)
17998#define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)
17999#define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
18000#define ETH_PTPTSLUR_TSUSS_Pos (0U)
18001#define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)
18002#define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
18003
18004/* Bit definition for Ethernet PTP Time Stamp Addend Register */
18005#define ETH_PTPTSAR_TSA_Pos (0U)
18006#define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)
18007#define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
18008
18009/* Bit definition for Ethernet PTP Target Time High Register */
18010#define ETH_PTPTTHR_TTSH_Pos (0U)
18011#define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)
18012#define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
18013
18014/* Bit definition for Ethernet PTP Target Time Low Register */
18015#define ETH_PTPTTLR_TTSL_Pos (0U)
18016#define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)
18017#define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
18018
18019/* Bit definition for Ethernet PTP Time Stamp Status Register */
18020#define ETH_PTPTSSR_TSTTR_Pos (5U)
18021#define ETH_PTPTSSR_TSTTR_Msk (0x1UL << ETH_PTPTSSR_TSTTR_Pos)
18022#define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
18023#define ETH_PTPTSSR_TSSO_Pos (4U)
18024#define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos)
18025#define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
18026
18027/******************************************************************************/
18028/* Ethernet DMA Registers bits definition */
18029/******************************************************************************/
18030
18031/* Bit definition for Ethernet DMA Bus Mode Register */
18032#define ETH_DMABMR_MB_Pos (26U)
18033#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos)
18034#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */
18035#define ETH_DMABMR_AAB_Pos (25U)
18036#define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)
18037#define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
18038#define ETH_DMABMR_FPM_Pos (24U)
18039#define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)
18040#define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
18041#define ETH_DMABMR_USP_Pos (23U)
18042#define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)
18043#define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
18044#define ETH_DMABMR_RDP_Pos (17U)
18045#define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)
18046#define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
18047#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18048#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18049#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18050#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18051#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18052#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18053#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18054#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18055#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18056#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18057#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18058#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18059#define ETH_DMABMR_FB_Pos (16U)
18060#define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)
18061#define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
18062#define ETH_DMABMR_RTPR_Pos (14U)
18063#define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)
18064#define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
18065#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
18066#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
18067#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
18068#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
18069#define ETH_DMABMR_PBL_Pos (8U)
18070#define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)
18071#define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
18072#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18073#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18074#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18075#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18076#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18077#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18078#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18079#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18080#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18081#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18082#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18083#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18084#define ETH_DMABMR_EDE_Pos (7U)
18085#define ETH_DMABMR_EDE_Msk (0x1UL << ETH_DMABMR_EDE_Pos)
18086#define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
18087#define ETH_DMABMR_DSL_Pos (2U)
18088#define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)
18089#define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
18090#define ETH_DMABMR_DA_Pos (1U)
18091#define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)
18092#define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
18093#define ETH_DMABMR_SR_Pos (0U)
18094#define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)
18095#define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
18096
18097/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18098#define ETH_DMATPDR_TPD_Pos (0U)
18099#define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)
18100#define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
18101
18102/* Bit definition for Ethernet DMA Receive Poll Demand Register */
18103#define ETH_DMARPDR_RPD_Pos (0U)
18104#define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)
18105#define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
18106
18107/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18108#define ETH_DMARDLAR_SRL_Pos (0U)
18109#define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)
18110#define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
18111
18112/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18113#define ETH_DMATDLAR_STL_Pos (0U)
18114#define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)
18115#define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
18116
18117/* Bit definition for Ethernet DMA Status Register */
18118#define ETH_DMASR_TSTS_Pos (29U)
18119#define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)
18120#define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
18121#define ETH_DMASR_PMTS_Pos (28U)
18122#define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)
18123#define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
18124#define ETH_DMASR_MMCS_Pos (27U)
18125#define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)
18126#define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
18127#define ETH_DMASR_EBS_Pos (23U)
18128#define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)
18129#define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
18130/* combination with EBS[2:0] for GetFlagStatus function */
18131#define ETH_DMASR_EBS_DescAccess_Pos (25U)
18132#define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)
18133#define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18134#define ETH_DMASR_EBS_ReadTransf_Pos (24U)
18135#define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)
18136#define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18137#define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
18138#define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)
18139#define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18140#define ETH_DMASR_TPS_Pos (20U)
18141#define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)
18142#define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
18143#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
18144#define ETH_DMASR_TPS_Fetching_Pos (20U)
18145#define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)
18146#define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18147#define ETH_DMASR_TPS_Waiting_Pos (21U)
18148#define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)
18149#define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18150#define ETH_DMASR_TPS_Reading_Pos (20U)
18151#define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)
18152#define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18153#define ETH_DMASR_TPS_Suspended_Pos (21U)
18154#define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)
18155#define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
18156#define ETH_DMASR_TPS_Closing_Pos (20U)
18157#define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)
18158#define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18159#define ETH_DMASR_RPS_Pos (17U)
18160#define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)
18161#define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
18162#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
18163#define ETH_DMASR_RPS_Fetching_Pos (17U)
18164#define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)
18165#define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18166#define ETH_DMASR_RPS_Waiting_Pos (17U)
18167#define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)
18168#define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18169#define ETH_DMASR_RPS_Suspended_Pos (19U)
18170#define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)
18171#define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18172#define ETH_DMASR_RPS_Closing_Pos (17U)
18173#define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)
18174#define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18175#define ETH_DMASR_RPS_Queuing_Pos (17U)
18176#define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)
18177#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
18178#define ETH_DMASR_NIS_Pos (16U)
18179#define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)
18180#define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
18181#define ETH_DMASR_AIS_Pos (15U)
18182#define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)
18183#define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
18184#define ETH_DMASR_ERS_Pos (14U)
18185#define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)
18186#define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
18187#define ETH_DMASR_FBES_Pos (13U)
18188#define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)
18189#define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
18190#define ETH_DMASR_ETS_Pos (10U)
18191#define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)
18192#define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
18193#define ETH_DMASR_RWTS_Pos (9U)
18194#define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)
18195#define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
18196#define ETH_DMASR_RPSS_Pos (8U)
18197#define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)
18198#define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
18199#define ETH_DMASR_RBUS_Pos (7U)
18200#define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)
18201#define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
18202#define ETH_DMASR_RS_Pos (6U)
18203#define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)
18204#define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
18205#define ETH_DMASR_TUS_Pos (5U)
18206#define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)
18207#define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
18208#define ETH_DMASR_ROS_Pos (4U)
18209#define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)
18210#define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
18211#define ETH_DMASR_TJTS_Pos (3U)
18212#define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)
18213#define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
18214#define ETH_DMASR_TBUS_Pos (2U)
18215#define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)
18216#define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
18217#define ETH_DMASR_TPSS_Pos (1U)
18218#define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)
18219#define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
18220#define ETH_DMASR_TS_Pos (0U)
18221#define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)
18222#define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
18223
18224/* Bit definition for Ethernet DMA Operation Mode Register */
18225#define ETH_DMAOMR_DTCEFD_Pos (26U)
18226#define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)
18227#define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
18228#define ETH_DMAOMR_RSF_Pos (25U)
18229#define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)
18230#define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
18231#define ETH_DMAOMR_DFRF_Pos (24U)
18232#define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)
18233#define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
18234#define ETH_DMAOMR_TSF_Pos (21U)
18235#define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)
18236#define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
18237#define ETH_DMAOMR_FTF_Pos (20U)
18238#define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)
18239#define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
18240#define ETH_DMAOMR_TTC_Pos (14U)
18241#define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)
18242#define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
18243#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18244#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18245#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18246#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18247#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18248#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18249#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18250#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18251#define ETH_DMAOMR_ST_Pos (13U)
18252#define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)
18253#define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
18254#define ETH_DMAOMR_FEF_Pos (7U)
18255#define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)
18256#define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
18257#define ETH_DMAOMR_FUGF_Pos (6U)
18258#define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)
18259#define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
18260#define ETH_DMAOMR_RTC_Pos (3U)
18261#define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)
18262#define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
18263#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
18264#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
18265#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
18266#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
18267#define ETH_DMAOMR_OSF_Pos (2U)
18268#define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)
18269#define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
18270#define ETH_DMAOMR_SR_Pos (1U)
18271#define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)
18272#define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
18273
18274/* Bit definition for Ethernet DMA Interrupt Enable Register */
18275#define ETH_DMAIER_NISE_Pos (16U)
18276#define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)
18277#define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
18278#define ETH_DMAIER_AISE_Pos (15U)
18279#define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)
18280#define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
18281#define ETH_DMAIER_ERIE_Pos (14U)
18282#define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)
18283#define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
18284#define ETH_DMAIER_FBEIE_Pos (13U)
18285#define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)
18286#define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
18287#define ETH_DMAIER_ETIE_Pos (10U)
18288#define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)
18289#define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
18290#define ETH_DMAIER_RWTIE_Pos (9U)
18291#define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)
18292#define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
18293#define ETH_DMAIER_RPSIE_Pos (8U)
18294#define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)
18295#define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
18296#define ETH_DMAIER_RBUIE_Pos (7U)
18297#define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)
18298#define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
18299#define ETH_DMAIER_RIE_Pos (6U)
18300#define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)
18301#define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
18302#define ETH_DMAIER_TUIE_Pos (5U)
18303#define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)
18304#define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
18305#define ETH_DMAIER_ROIE_Pos (4U)
18306#define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)
18307#define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
18308#define ETH_DMAIER_TJTIE_Pos (3U)
18309#define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)
18310#define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
18311#define ETH_DMAIER_TBUIE_Pos (2U)
18312#define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)
18313#define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
18314#define ETH_DMAIER_TPSIE_Pos (1U)
18315#define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)
18316#define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
18317#define ETH_DMAIER_TIE_Pos (0U)
18318#define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)
18319#define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
18320
18321/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18322#define ETH_DMAMFBOCR_OFOC_Pos (28U)
18323#define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)
18324#define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
18325#define ETH_DMAMFBOCR_MFA_Pos (17U)
18326#define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)
18327#define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
18328#define ETH_DMAMFBOCR_OMFC_Pos (16U)
18329#define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)
18330#define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
18331#define ETH_DMAMFBOCR_MFC_Pos (0U)
18332#define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)
18333#define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
18334
18335/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18336#define ETH_DMACHTDR_HTDAP_Pos (0U)
18337#define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)
18338#define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
18339
18340/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18341#define ETH_DMACHRDR_HRDAP_Pos (0U)
18342#define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)
18343#define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
18344
18345/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18346#define ETH_DMACHTBAR_HTBAP_Pos (0U)
18347#define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)
18348#define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
18349
18350/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18351#define ETH_DMACHRBAR_HRBAP_Pos (0U)
18352#define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)
18353#define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
18354
18355/******************************************************************************/
18356/* */
18357/* USB_OTG */
18358/* */
18359/******************************************************************************/
18360/******************** Bit definition for USB_OTG_GOTGCTL register ***********/
18361#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18362#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
18363#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
18364#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18365#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
18366#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
18367#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18368#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
18369#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
18370#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18371#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
18372#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
18373#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18374#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
18375#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
18376#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18377#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
18378#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
18379#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18380#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
18381#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
18382#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18383#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
18384#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
18385#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
18386#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
18387#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
18388#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
18389#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
18390#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
18391#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
18392#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
18393#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
18394#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
18395#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
18396#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
18397#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
18398#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
18399#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
18400#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
18401#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
18402#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
18403#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
18404#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
18405#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
18406#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
18407#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
18408#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
18409#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18410#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
18411#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
18412#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
18413#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
18414#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
18415
18416/******************** Bit definition forUSB_OTG_HCFG register ********************/
18418#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18419#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
18420#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
18421#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
18422#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
18423#define USB_OTG_HCFG_FSLSS_Pos (2U)
18424#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
18425#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
18426
18427/******************** Bit definition for USB_OTG_DCFG register ********************/
18429#define USB_OTG_DCFG_DSPD_Pos (0U)
18430#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
18431#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
18432#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
18433#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
18434#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18435#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
18436#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
18438#define USB_OTG_DCFG_DAD_Pos (4U)
18439#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
18440#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
18441#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
18442#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
18443#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
18444#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
18445#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
18446#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
18447#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
18449#define USB_OTG_DCFG_PFIVL_Pos (11U)
18450#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
18451#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
18452#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
18453#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
18455#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
18456#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
18457#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
18459#define USB_OTG_DCFG_ERRATIM_Pos (15U)
18460#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
18461#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
18463#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18464#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18465#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
18466#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18467#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
18468
18469/******************** Bit definition for USB_OTG_PCGCR register ********************/
18470#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18471#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
18472#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
18473#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18474#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
18475#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
18476#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18477#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
18478#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
18479
18480/******************** Bit definition for USB_OTG_GOTGINT register ********************/
18481#define USB_OTG_GOTGINT_SEDET_Pos (2U)
18482#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
18483#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
18484#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18485#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
18486#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
18487#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18488#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
18489#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
18490#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18491#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
18492#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
18493#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18494#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
18495#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
18496#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18497#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
18498#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
18499#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
18500#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
18501#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
18502
18503/******************** Bit definition for USB_OTG_DCTL register ********************/
18504#define USB_OTG_DCTL_RWUSIG_Pos (0U)
18505#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
18506#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
18507#define USB_OTG_DCTL_SDIS_Pos (1U)
18508#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
18509#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
18510#define USB_OTG_DCTL_GINSTS_Pos (2U)
18511#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
18512#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
18513#define USB_OTG_DCTL_GONSTS_Pos (3U)
18514#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
18515#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
18517#define USB_OTG_DCTL_TCTL_Pos (4U)
18518#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
18519#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
18520#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
18521#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
18522#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
18523#define USB_OTG_DCTL_SGINAK_Pos (7U)
18524#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
18525#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
18526#define USB_OTG_DCTL_CGINAK_Pos (8U)
18527#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
18528#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
18529#define USB_OTG_DCTL_SGONAK_Pos (9U)
18530#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
18531#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
18532#define USB_OTG_DCTL_CGONAK_Pos (10U)
18533#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
18534#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
18535#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18536#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
18537#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
18538
18539/******************** Bit definition for USB_OTG_HFIR register ********************/
18540#define USB_OTG_HFIR_FRIVL_Pos (0U)
18541#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
18542#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
18543
18544/******************** Bit definition for USB_OTG_HFNUM register ********************/
18545#define USB_OTG_HFNUM_FRNUM_Pos (0U)
18546#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
18547#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
18548#define USB_OTG_HFNUM_FTREM_Pos (16U)
18549#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
18550#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
18551
18552/******************** Bit definition for USB_OTG_DSTS register ********************/
18553#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18554#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
18555#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
18557#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18558#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
18559#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
18560#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
18561#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
18562#define USB_OTG_DSTS_EERR_Pos (3U)
18563#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
18564#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
18565#define USB_OTG_DSTS_FNSOF_Pos (8U)
18566#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
18567#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
18568
18569/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18570#define USB_OTG_GAHBCFG_GINT_Pos (0U)
18571#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
18572#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
18573#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18574#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18575#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
18576#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18577#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18578#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18579#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18580#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
18581#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18582#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
18583#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
18584#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18585#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
18586#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
18587#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18588#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
18589#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
18590
18591/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18593#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18594#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18595#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
18596#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18597#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18598#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
18599#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18600#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
18601#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
18602#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18603#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
18604#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
18605#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18606#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
18607#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
18608#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18609#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
18610#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
18611#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
18612#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
18613#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
18614#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
18615#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18616#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
18617#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
18618#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18619#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
18620#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
18621#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18622#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
18623#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
18624#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18625#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
18626#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
18627#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18628#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
18629#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
18630#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18631#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
18632#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
18633#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18634#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
18635#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
18636#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18637#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
18638#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
18639#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18640#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
18641#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
18642#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18643#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
18644#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
18645#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18646#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
18647#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
18648#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18649#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
18650#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
18651#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18652#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
18653#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
18654
18655/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18656#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18657#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
18658#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
18659#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18660#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
18661#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
18662#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18663#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
18664#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
18665#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18666#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
18667#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
18668#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18669#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
18670#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
18671
18673#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18674#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18675#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
18676#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18677#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18678#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18679#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18680#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
18681#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18682#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
18683#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
18684#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18685#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
18686#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
18687
18688/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18689#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18690#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
18691#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
18692#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18693#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
18694#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
18695#define USB_OTG_DIEPMSK_TOM_Pos (3U)
18696#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
18697#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
18698#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18699#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
18700#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
18701#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18702#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
18703#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
18704#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18705#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
18706#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
18707#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18708#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
18709#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
18710#define USB_OTG_DIEPMSK_NAKM_Pos (13U)
18711#define USB_OTG_DIEPMSK_NAKM_Msk (0x1UL << USB_OTG_DIEPMSK_NAKM_Pos)
18712#define USB_OTG_DIEPMSK_NAKM USB_OTG_DIEPMSK_NAKM_Msk
18713
18714/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18715#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18716#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
18717#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
18718#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
18719#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18720#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
18721#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18722#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18723#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18724#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18725#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18726#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18727#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18728#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
18730#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
18731#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18732#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
18733#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18734#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18735#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18736#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18737#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18738#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18739#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18740#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
18741
18742/******************** Bit definition for USB_OTG_HAINT register ********************/
18743#define USB_OTG_HAINT_HAINT_Pos (0U)
18744#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
18745#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
18746
18747/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
18748#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
18749#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
18750#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
18751#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
18752#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
18753#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
18754#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
18755#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
18756#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
18757#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
18758#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
18759#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
18760#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
18761#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
18762#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
18763#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
18764#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
18765#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
18766#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
18767#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
18768#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
18769#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
18770#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
18771#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
18772#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
18773#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
18774#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
18775#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
18776#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
18777#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
18778#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
18779#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
18780#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
18781#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
18782#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
18783#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
18784/******************** Bit definition for USB_OTG_GINTSTS register ********************/
18785#define USB_OTG_GINTSTS_CMOD_Pos (0U)
18786#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
18787#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
18788#define USB_OTG_GINTSTS_MMIS_Pos (1U)
18789#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
18790#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
18791#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
18792#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
18793#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
18794#define USB_OTG_GINTSTS_SOF_Pos (3U)
18795#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
18796#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
18797#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
18798#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
18799#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
18800#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
18801#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
18802#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
18803#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
18804#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
18805#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
18806#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
18807#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
18808#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
18809#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
18810#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
18811#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
18812#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
18813#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
18814#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
18815#define USB_OTG_GINTSTS_USBRST_Pos (12U)
18816#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
18817#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
18818#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
18819#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
18820#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
18821#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
18822#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
18823#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
18824#define USB_OTG_GINTSTS_EOPF_Pos (15U)
18825#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
18826#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
18827#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
18828#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
18829#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
18830#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
18831#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
18832#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
18833#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
18834#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
18835#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
18836#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
18837#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
18838#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
18839#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
18840#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
18841#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
18842#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
18843#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
18844#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
18845#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
18846#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
18847#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
18848#define USB_OTG_GINTSTS_HCINT_Pos (25U)
18849#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
18850#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
18851#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
18852#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
18853#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
18854#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
18855#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
18856#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
18857#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
18858#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
18859#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
18860#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
18861#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
18862#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
18863#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
18864#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
18865#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
18866#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
18867#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
18868#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
18869
18870/******************** Bit definition for USB_OTG_GINTMSK register ********************/
18871#define USB_OTG_GINTMSK_MMISM_Pos (1U)
18872#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
18873#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
18874#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
18875#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
18876#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
18877#define USB_OTG_GINTMSK_SOFM_Pos (3U)
18878#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
18879#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
18880#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
18881#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
18882#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
18883#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
18884#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
18885#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
18886#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
18887#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
18888#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
18889#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
18890#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
18891#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
18892#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
18893#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
18894#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
18895#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
18896#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
18897#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
18898#define USB_OTG_GINTMSK_USBRST_Pos (12U)
18899#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
18900#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
18901#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
18902#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
18903#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
18904#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
18905#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
18906#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
18907#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
18908#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
18909#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
18910#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
18911#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
18912#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
18913#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
18914#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
18915#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
18916#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
18917#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
18918#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
18919#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
18920#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
18921#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
18922#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
18923#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
18924#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
18925#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
18926#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
18927#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
18928#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
18929#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
18930#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
18931#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
18932#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
18933#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
18934#define USB_OTG_GINTMSK_HCIM_Pos (25U)
18935#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
18936#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
18937#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
18938#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
18939#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
18940#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
18941#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
18942#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
18943#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
18944#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
18945#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
18946#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
18947#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
18948#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
18949#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
18950#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
18951#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
18952#define USB_OTG_GINTMSK_WUIM_Pos (31U)
18953#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
18954#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
18955
18956/******************** Bit definition for USB_OTG_DAINT register ********************/
18957#define USB_OTG_DAINT_IEPINT_Pos (0U)
18958#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
18959#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
18960#define USB_OTG_DAINT_OEPINT_Pos (16U)
18961#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
18962#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
18963
18964/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
18965#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
18966#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
18967#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
18968
18969/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
18970#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
18971#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
18972#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
18973#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
18974#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
18975#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
18976#define USB_OTG_GRXSTSP_DPID_Pos (15U)
18977#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
18978#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
18979#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
18980#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
18981#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
18982
18983/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
18984#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
18985#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
18986#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
18987#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
18988#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
18989#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
18990
18991/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
18992#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
18993#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
18994#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
18995
18996/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
18997#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
18998#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
18999#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
19000
19001/******************** Bit definition for OTG register ********************/
19002#define USB_OTG_NPTXFSA_Pos (0U)
19003#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
19004#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
19005#define USB_OTG_NPTXFD_Pos (16U)
19006#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
19007#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
19008#define USB_OTG_TX0FSA_Pos (0U)
19009#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
19010#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
19011#define USB_OTG_TX0FD_Pos (16U)
19012#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
19013#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
19014
19015/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
19016#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
19017#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
19018#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
19019
19020/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
19021#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19022#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
19023#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
19025#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19026#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19027#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
19028#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19029#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19030#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19031#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19032#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19033#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19034#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19035#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
19037#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19038#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19039#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
19040#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19041#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19042#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19043#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19044#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19045#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19046#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
19047
19048/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
19049#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19050#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
19051#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
19052#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19053#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
19054#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
19056#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19057#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19058#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
19059#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19060#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19061#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19062#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19063#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19064#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19065#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19066#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19067#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
19068#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19069#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
19070#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
19072#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19073#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19074#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
19075#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19076#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19077#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19078#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19079#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19080#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19081#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19082#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19083#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
19084#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19085#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
19086#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
19087
19088/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
19089#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19090#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
19091#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
19092
19093/******************** Bit definition for USB_OTG_DEACHINT register ********************/
19094#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19095#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
19096#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
19097#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19098#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
19099#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
19100
19101/******************** Bit definition for USB_OTG_GCCFG register ********************/
19102#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19103#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
19104#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
19105#define USB_OTG_GCCFG_VBDEN_Pos (21U)
19106#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
19107#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
19108
19109/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
19110#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19111#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
19112#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
19113#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19114#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
19115#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
19116
19117/******************** Bit definition for USB_OTG_CID register ********************/
19118#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19119#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
19120#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
19121
19122/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19123#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19124#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
19125#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
19126#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19127#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
19128#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
19129#define USB_OTG_GLPMCFG_BESL_Pos (2U)
19130#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
19131#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
19132#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19133#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
19134#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
19135#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19136#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
19137#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
19138#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19139#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
19140#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
19141#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19142#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
19143#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
19144#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19145#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
19146#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
19147#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19148#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
19149#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
19150#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
19151#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
19152#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
19153#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19154#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
19155#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
19156#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19157#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
19158#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
19159#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19160#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
19161#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
19162#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19163#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
19164#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
19165#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19166#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
19167#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
19168
19169/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19170#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19171#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
19172#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
19173#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19174#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
19175#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
19176#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19177#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
19178#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
19179#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19180#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
19181#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
19182#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19183#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
19184#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
19185#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19186#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
19187#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
19188#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19189#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
19190#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
19191#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19192#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
19193#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
19194#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19195#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
19196#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
19197
19198/******************** Bit definition for USB_OTG_HPRT register ********************/
19199#define USB_OTG_HPRT_PCSTS_Pos (0U)
19200#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
19201#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
19202#define USB_OTG_HPRT_PCDET_Pos (1U)
19203#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
19204#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
19205#define USB_OTG_HPRT_PENA_Pos (2U)
19206#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
19207#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
19208#define USB_OTG_HPRT_PENCHNG_Pos (3U)
19209#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
19210#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
19211#define USB_OTG_HPRT_POCA_Pos (4U)
19212#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
19213#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
19214#define USB_OTG_HPRT_POCCHNG_Pos (5U)
19215#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
19216#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
19217#define USB_OTG_HPRT_PRES_Pos (6U)
19218#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
19219#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
19220#define USB_OTG_HPRT_PSUSP_Pos (7U)
19221#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
19222#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
19223#define USB_OTG_HPRT_PRST_Pos (8U)
19224#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
19225#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
19227#define USB_OTG_HPRT_PLSTS_Pos (10U)
19228#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
19229#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
19230#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
19231#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
19232#define USB_OTG_HPRT_PPWR_Pos (12U)
19233#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
19234#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
19236#define USB_OTG_HPRT_PTCTL_Pos (13U)
19237#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
19238#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
19239#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
19240#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
19241#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
19242#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
19244#define USB_OTG_HPRT_PSPD_Pos (17U)
19245#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
19246#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
19247#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
19248#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
19249
19250/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19251#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19252#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
19253#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
19254#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19255#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
19256#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
19257#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19258#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
19259#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
19260#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19261#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
19262#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
19263#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19264#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
19265#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
19266#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19267#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
19268#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
19269#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19270#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
19271#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
19272#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19273#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
19274#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
19275#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19276#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
19277#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
19278#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19279#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
19280#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
19281#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19282#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
19283#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
19284
19285/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19286#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19287#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
19288#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
19289#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19290#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
19291#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
19292
19293/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19294#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19295#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
19296#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
19297#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19298#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
19299#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
19300#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19301#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
19302#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
19303#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19304#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
19305#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
19307#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19308#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19309#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
19310#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19311#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
19312#define USB_OTG_DIEPCTL_STALL_Pos (21U)
19313#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
19314#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
19316#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19317#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19318#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
19319#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19320#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19321#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19322#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
19323#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19324#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
19325#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
19326#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19327#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
19328#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
19329#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19330#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
19331#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
19332#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19333#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
19334#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
19335#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19336#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
19337#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
19338#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19339#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
19340#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
19341
19342/******************** Bit definition for USB_OTG_HCCHAR register ********************/
19343#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19344#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
19345#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
19347#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19348#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
19349#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
19350#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
19351#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
19352#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
19353#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
19354#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19355#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
19356#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
19357#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19358#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
19359#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
19361#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19362#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
19363#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
19364#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
19365#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
19367#define USB_OTG_HCCHAR_MC_Pos (20U)
19368#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
19369#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
19370#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
19371#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
19373#define USB_OTG_HCCHAR_DAD_Pos (22U)
19374#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
19375#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
19376#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
19377#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
19378#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
19379#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
19380#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
19381#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
19382#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
19383#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19384#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
19385#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
19386#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19387#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
19388#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
19389#define USB_OTG_HCCHAR_CHENA_Pos (31U)
19390#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
19391#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
19392
19393/******************** Bit definition for USB_OTG_HCSPLT register ********************/
19395#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19396#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
19397#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
19398#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19399#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19400#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19401#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19402#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19403#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19404#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
19406#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19407#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
19408#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
19409#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19410#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19411#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19412#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19413#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19414#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19415#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
19417#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19418#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19419#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
19420#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19421#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
19422#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19423#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
19424#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
19425#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19426#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
19427#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
19428
19429/******************** Bit definition for USB_OTG_HCINT register ********************/
19430#define USB_OTG_HCINT_XFRC_Pos (0U)
19431#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
19432#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
19433#define USB_OTG_HCINT_CHH_Pos (1U)
19434#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
19435#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
19436#define USB_OTG_HCINT_AHBERR_Pos (2U)
19437#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
19438#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
19439#define USB_OTG_HCINT_STALL_Pos (3U)
19440#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
19441#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
19442#define USB_OTG_HCINT_NAK_Pos (4U)
19443#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
19444#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
19445#define USB_OTG_HCINT_ACK_Pos (5U)
19446#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
19447#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
19448#define USB_OTG_HCINT_NYET_Pos (6U)
19449#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
19450#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
19451#define USB_OTG_HCINT_TXERR_Pos (7U)
19452#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
19453#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
19454#define USB_OTG_HCINT_BBERR_Pos (8U)
19455#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
19456#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
19457#define USB_OTG_HCINT_FRMOR_Pos (9U)
19458#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
19459#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
19460#define USB_OTG_HCINT_DTERR_Pos (10U)
19461#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
19462#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
19463
19464/******************** Bit definition for USB_OTG_DIEPINT register ********************/
19465#define USB_OTG_DIEPINT_XFRC_Pos (0U)
19466#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
19467#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
19468#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19469#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
19470#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
19471#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
19472#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
19473#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
19474#define USB_OTG_DIEPINT_TOC_Pos (3U)
19475#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
19476#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
19477#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19478#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
19479#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
19480#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
19481#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
19482#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
19483#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19484#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
19485#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
19486#define USB_OTG_DIEPINT_TXFE_Pos (7U)
19487#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
19488#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
19489#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19490#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
19491#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
19492#define USB_OTG_DIEPINT_BNA_Pos (9U)
19493#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
19494#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
19495#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19496#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
19497#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
19498#define USB_OTG_DIEPINT_BERR_Pos (12U)
19499#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
19500#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
19501#define USB_OTG_DIEPINT_NAK_Pos (13U)
19502#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
19503#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
19504
19505/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
19506#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19507#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
19508#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
19509#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19510#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
19511#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
19512#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19513#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
19514#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
19515#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19516#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
19517#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
19518#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19519#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
19520#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
19521#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19522#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
19523#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
19524#define USB_OTG_HCINTMSK_NYET_Pos (6U)
19525#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
19526#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
19527#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19528#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
19529#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
19530#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19531#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
19532#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
19533#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19534#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
19535#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
19536#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19537#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
19538#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
19539
19540/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19542#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19543#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
19544#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
19545#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19546#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
19547#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
19548#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19549#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
19550#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
19551/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19552#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19553#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
19554#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
19555#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19556#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
19557#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
19558#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19559#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
19560#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
19561#define USB_OTG_HCTSIZ_DPID_Pos (29U)
19562#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
19563#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
19564#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
19565#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
19566
19567/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19568#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19569#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
19570#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
19571
19572/******************** Bit definition for USB_OTG_HCDMA register ********************/
19573#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19574#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
19575#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
19576
19577/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19578#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19579#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
19580#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
19581
19582/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19583#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19584#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
19585#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
19586#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19587#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
19588#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
19589
19590/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19592#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19593#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
19594#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
19595#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19596#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
19597#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
19598#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19599#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
19600#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
19601#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19602#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
19603#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
19604#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19605#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
19606#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
19607#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19608#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19609#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
19610#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19611#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
19612#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19613#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
19614#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
19615#define USB_OTG_DOEPCTL_STALL_Pos (21U)
19616#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
19617#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
19618#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19619#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
19620#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
19621#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19622#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
19623#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
19624#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19625#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
19626#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
19627#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19628#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
19629#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
19630
19631/******************** Bit definition for USB_OTG_DOEPINT register ********************/
19632#define USB_OTG_DOEPINT_XFRC_Pos (0U)
19633#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
19634#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
19635#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19636#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
19637#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
19638#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
19639#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
19640#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
19641#define USB_OTG_DOEPINT_STUP_Pos (3U)
19642#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
19643#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
19644#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19645#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
19646#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
19647#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
19648#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
19649#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
19650#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19651#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
19652#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
19653#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
19654#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
19655#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
19656#define USB_OTG_DOEPINT_NAK_Pos (13U)
19657#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
19658#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
19659#define USB_OTG_DOEPINT_NYET_Pos (14U)
19660#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
19661#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
19662#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
19663#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
19664#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
19665/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19667#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19668#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
19669#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
19670#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19671#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
19672#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
19674#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19675#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19676#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
19677#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19678#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
19679
19680/******************** Bit definition for PCGCCTL register ********************/
19681#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
19682#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
19683#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
19684#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
19685#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
19686#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
19687#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19688#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
19689#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
19690
19691/* Legacy define */
19692/******************** Bit definition for OTG register ********************/
19693#define USB_OTG_CHNUM_Pos (0U)
19694#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
19695#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
19696#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
19697#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
19698#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
19699#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
19700#define USB_OTG_BCNT_Pos (4U)
19701#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
19702#define USB_OTG_BCNT USB_OTG_BCNT_Msk
19704#define USB_OTG_DPID_Pos (15U)
19705#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
19706#define USB_OTG_DPID USB_OTG_DPID_Msk
19707#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
19708#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
19710#define USB_OTG_PKTSTS_Pos (17U)
19711#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
19712#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
19713#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
19714#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
19715#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
19716#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
19718#define USB_OTG_EPNUM_Pos (0U)
19719#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
19720#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
19721#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
19722#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
19723#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
19724#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
19726#define USB_OTG_FRMNUM_Pos (21U)
19727#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
19728#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
19729#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
19730#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
19731#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
19732#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
19736
19740
19744
19745/******************************* ADC Instances ********************************/
19746#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19747 ((INSTANCE) == ADC2) || \
19748 ((INSTANCE) == ADC3))
19750#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19752#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
19753
19754/******************************* CAN Instances ********************************/
19755#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
19756 ((INSTANCE) == CAN2))
19757/******************************* CRC Instances ********************************/
19758#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19759
19760/******************************* DAC Instances ********************************/
19761#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19762
19763/******************************* DCMI Instances *******************************/
19764#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19765
19766/******************************* DMA2D Instances *******************************/
19767#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19768
19769/******************************** DMA Instances *******************************/
19770#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
19771 ((INSTANCE) == DMA1_Stream1) || \
19772 ((INSTANCE) == DMA1_Stream2) || \
19773 ((INSTANCE) == DMA1_Stream3) || \
19774 ((INSTANCE) == DMA1_Stream4) || \
19775 ((INSTANCE) == DMA1_Stream5) || \
19776 ((INSTANCE) == DMA1_Stream6) || \
19777 ((INSTANCE) == DMA1_Stream7) || \
19778 ((INSTANCE) == DMA2_Stream0) || \
19779 ((INSTANCE) == DMA2_Stream1) || \
19780 ((INSTANCE) == DMA2_Stream2) || \
19781 ((INSTANCE) == DMA2_Stream3) || \
19782 ((INSTANCE) == DMA2_Stream4) || \
19783 ((INSTANCE) == DMA2_Stream5) || \
19784 ((INSTANCE) == DMA2_Stream6) || \
19785 ((INSTANCE) == DMA2_Stream7))
19786
19787/******************************* GPIO Instances *******************************/
19788#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19789 ((INSTANCE) == GPIOB) || \
19790 ((INSTANCE) == GPIOC) || \
19791 ((INSTANCE) == GPIOD) || \
19792 ((INSTANCE) == GPIOE) || \
19793 ((INSTANCE) == GPIOF) || \
19794 ((INSTANCE) == GPIOG) || \
19795 ((INSTANCE) == GPIOH) || \
19796 ((INSTANCE) == GPIOI) || \
19797 ((INSTANCE) == GPIOJ) || \
19798 ((INSTANCE) == GPIOK))
19799
19800/******************************** I2C Instances *******************************/
19801#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19802 ((INSTANCE) == I2C2) || \
19803 ((INSTANCE) == I2C3))
19804
19805/******************************* SMBUS Instances ******************************/
19806#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
19807
19808/******************************** I2S Instances *******************************/
19810#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
19811 ((INSTANCE) == SPI3))
19812
19813/*************************** I2S Extended Instances ***************************/
19814#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
19815 ((INSTANCE) == I2S3ext))
19816/* Legacy Defines */
19817#define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
19818
19819/****************************** LTDC Instances ********************************/
19820#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
19821/******************************* RNG Instances ********************************/
19822#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
19823
19824/****************************** RTC Instances *********************************/
19825#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
19826
19827/******************************* SAI Instances ********************************/
19828#define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
19829 ((PERIPH) == SAI1_Block_B))
19830/* Legacy define */
19832#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
19833
19834/******************************** SPI Instances *******************************/
19835#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
19836 ((INSTANCE) == SPI2) || \
19837 ((INSTANCE) == SPI3) || \
19838 ((INSTANCE) == SPI4) || \
19839 ((INSTANCE) == SPI5) || \
19840 ((INSTANCE) == SPI6))
19841
19842
19843/****************** TIM Instances : All supported instances *******************/
19844#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19845 ((INSTANCE) == TIM2) || \
19846 ((INSTANCE) == TIM3) || \
19847 ((INSTANCE) == TIM4) || \
19848 ((INSTANCE) == TIM5) || \
19849 ((INSTANCE) == TIM6) || \
19850 ((INSTANCE) == TIM7) || \
19851 ((INSTANCE) == TIM8) || \
19852 ((INSTANCE) == TIM9) || \
19853 ((INSTANCE) == TIM10)|| \
19854 ((INSTANCE) == TIM11)|| \
19855 ((INSTANCE) == TIM12)|| \
19856 ((INSTANCE) == TIM13)|| \
19857 ((INSTANCE) == TIM14))
19858
19859/************* TIM Instances : at least 1 capture/compare channel *************/
19860#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19861 ((INSTANCE) == TIM2) || \
19862 ((INSTANCE) == TIM3) || \
19863 ((INSTANCE) == TIM4) || \
19864 ((INSTANCE) == TIM5) || \
19865 ((INSTANCE) == TIM8) || \
19866 ((INSTANCE) == TIM9) || \
19867 ((INSTANCE) == TIM10) || \
19868 ((INSTANCE) == TIM11) || \
19869 ((INSTANCE) == TIM12) || \
19870 ((INSTANCE) == TIM13) || \
19871 ((INSTANCE) == TIM14))
19872
19873/************ TIM Instances : at least 2 capture/compare channels *************/
19874#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19875 ((INSTANCE) == TIM2) || \
19876 ((INSTANCE) == TIM3) || \
19877 ((INSTANCE) == TIM4) || \
19878 ((INSTANCE) == TIM5) || \
19879 ((INSTANCE) == TIM8) || \
19880 ((INSTANCE) == TIM9) || \
19881 ((INSTANCE) == TIM12))
19882
19883/************ TIM Instances : at least 3 capture/compare channels *************/
19884#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19885 ((INSTANCE) == TIM2) || \
19886 ((INSTANCE) == TIM3) || \
19887 ((INSTANCE) == TIM4) || \
19888 ((INSTANCE) == TIM5) || \
19889 ((INSTANCE) == TIM8))
19890
19891/************ TIM Instances : at least 4 capture/compare channels *************/
19892#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19893 ((INSTANCE) == TIM2) || \
19894 ((INSTANCE) == TIM3) || \
19895 ((INSTANCE) == TIM4) || \
19896 ((INSTANCE) == TIM5) || \
19897 ((INSTANCE) == TIM8))
19898
19899/******************** TIM Instances : Advanced-control timers *****************/
19900#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19901 ((INSTANCE) == TIM8))
19902
19903/******************* TIM Instances : Timer input XOR function *****************/
19904#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19905 ((INSTANCE) == TIM2) || \
19906 ((INSTANCE) == TIM3) || \
19907 ((INSTANCE) == TIM4) || \
19908 ((INSTANCE) == TIM5) || \
19909 ((INSTANCE) == TIM8))
19910
19911/****************** TIM Instances : DMA requests generation (UDE) *************/
19912#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19913 ((INSTANCE) == TIM2) || \
19914 ((INSTANCE) == TIM3) || \
19915 ((INSTANCE) == TIM4) || \
19916 ((INSTANCE) == TIM5) || \
19917 ((INSTANCE) == TIM6) || \
19918 ((INSTANCE) == TIM7) || \
19919 ((INSTANCE) == TIM8))
19920
19921/************ TIM Instances : DMA requests generation (CCxDE) *****************/
19922#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19923 ((INSTANCE) == TIM2) || \
19924 ((INSTANCE) == TIM3) || \
19925 ((INSTANCE) == TIM4) || \
19926 ((INSTANCE) == TIM5) || \
19927 ((INSTANCE) == TIM8))
19928
19929/************ TIM Instances : DMA requests generation (COMDE) *****************/
19930#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19931 ((INSTANCE) == TIM2) || \
19932 ((INSTANCE) == TIM3) || \
19933 ((INSTANCE) == TIM4) || \
19934 ((INSTANCE) == TIM5) || \
19935 ((INSTANCE) == TIM8))
19936
19937/******************** TIM Instances : DMA burst feature ***********************/
19938#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19939 ((INSTANCE) == TIM2) || \
19940 ((INSTANCE) == TIM3) || \
19941 ((INSTANCE) == TIM4) || \
19942 ((INSTANCE) == TIM5) || \
19943 ((INSTANCE) == TIM8))
19944
19945/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
19946#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19947 ((INSTANCE) == TIM2) || \
19948 ((INSTANCE) == TIM3) || \
19949 ((INSTANCE) == TIM4) || \
19950 ((INSTANCE) == TIM5) || \
19951 ((INSTANCE) == TIM6) || \
19952 ((INSTANCE) == TIM7) || \
19953 ((INSTANCE) == TIM8))
19954
19955/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
19956#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19957 ((INSTANCE) == TIM2) || \
19958 ((INSTANCE) == TIM3) || \
19959 ((INSTANCE) == TIM4) || \
19960 ((INSTANCE) == TIM5) || \
19961 ((INSTANCE) == TIM8) || \
19962 ((INSTANCE) == TIM9) || \
19963 ((INSTANCE) == TIM12))
19964/********************** TIM Instances : 32 bit Counter ************************/
19965#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
19966 ((INSTANCE) == TIM5))
19967
19968/***************** TIM Instances : external trigger input available ************/
19969#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19970 ((INSTANCE) == TIM2) || \
19971 ((INSTANCE) == TIM3) || \
19972 ((INSTANCE) == TIM4) || \
19973 ((INSTANCE) == TIM5) || \
19974 ((INSTANCE) == TIM8))
19975
19976/****************** TIM Instances : remapping capability **********************/
19977#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
19978 ((INSTANCE) == TIM5) || \
19979 ((INSTANCE) == TIM11))
19980
19981/******************* TIM Instances : output(s) available **********************/
19982#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
19983 ((((INSTANCE) == TIM1) && \
19984 (((CHANNEL) == TIM_CHANNEL_1) || \
19985 ((CHANNEL) == TIM_CHANNEL_2) || \
19986 ((CHANNEL) == TIM_CHANNEL_3) || \
19987 ((CHANNEL) == TIM_CHANNEL_4))) \
19988 || \
19989 (((INSTANCE) == TIM2) && \
19990 (((CHANNEL) == TIM_CHANNEL_1) || \
19991 ((CHANNEL) == TIM_CHANNEL_2) || \
19992 ((CHANNEL) == TIM_CHANNEL_3) || \
19993 ((CHANNEL) == TIM_CHANNEL_4))) \
19994 || \
19995 (((INSTANCE) == TIM3) && \
19996 (((CHANNEL) == TIM_CHANNEL_1) || \
19997 ((CHANNEL) == TIM_CHANNEL_2) || \
19998 ((CHANNEL) == TIM_CHANNEL_3) || \
19999 ((CHANNEL) == TIM_CHANNEL_4))) \
20000 || \
20001 (((INSTANCE) == TIM4) && \
20002 (((CHANNEL) == TIM_CHANNEL_1) || \
20003 ((CHANNEL) == TIM_CHANNEL_2) || \
20004 ((CHANNEL) == TIM_CHANNEL_3) || \
20005 ((CHANNEL) == TIM_CHANNEL_4))) \
20006 || \
20007 (((INSTANCE) == TIM5) && \
20008 (((CHANNEL) == TIM_CHANNEL_1) || \
20009 ((CHANNEL) == TIM_CHANNEL_2) || \
20010 ((CHANNEL) == TIM_CHANNEL_3) || \
20011 ((CHANNEL) == TIM_CHANNEL_4))) \
20012 || \
20013 (((INSTANCE) == TIM8) && \
20014 (((CHANNEL) == TIM_CHANNEL_1) || \
20015 ((CHANNEL) == TIM_CHANNEL_2) || \
20016 ((CHANNEL) == TIM_CHANNEL_3) || \
20017 ((CHANNEL) == TIM_CHANNEL_4))) \
20018 || \
20019 (((INSTANCE) == TIM9) && \
20020 (((CHANNEL) == TIM_CHANNEL_1) || \
20021 ((CHANNEL) == TIM_CHANNEL_2))) \
20022 || \
20023 (((INSTANCE) == TIM10) && \
20024 (((CHANNEL) == TIM_CHANNEL_1))) \
20025 || \
20026 (((INSTANCE) == TIM11) && \
20027 (((CHANNEL) == TIM_CHANNEL_1))) \
20028 || \
20029 (((INSTANCE) == TIM12) && \
20030 (((CHANNEL) == TIM_CHANNEL_1) || \
20031 ((CHANNEL) == TIM_CHANNEL_2))) \
20032 || \
20033 (((INSTANCE) == TIM13) && \
20034 (((CHANNEL) == TIM_CHANNEL_1))) \
20035 || \
20036 (((INSTANCE) == TIM14) && \
20037 (((CHANNEL) == TIM_CHANNEL_1))))
20038
20039/************ TIM Instances : complementary output(s) available ***************/
20040#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20041 ((((INSTANCE) == TIM1) && \
20042 (((CHANNEL) == TIM_CHANNEL_1) || \
20043 ((CHANNEL) == TIM_CHANNEL_2) || \
20044 ((CHANNEL) == TIM_CHANNEL_3))) \
20045 || \
20046 (((INSTANCE) == TIM8) && \
20047 (((CHANNEL) == TIM_CHANNEL_1) || \
20048 ((CHANNEL) == TIM_CHANNEL_2) || \
20049 ((CHANNEL) == TIM_CHANNEL_3))))
20050
20051/****************** TIM Instances : supporting counting mode selection ********/
20052#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20053 ((INSTANCE) == TIM2) || \
20054 ((INSTANCE) == TIM3) || \
20055 ((INSTANCE) == TIM4) || \
20056 ((INSTANCE) == TIM5) || \
20057 ((INSTANCE) == TIM8))
20058
20059/****************** TIM Instances : supporting clock division *****************/
20060#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20061 ((INSTANCE) == TIM2) || \
20062 ((INSTANCE) == TIM3) || \
20063 ((INSTANCE) == TIM4) || \
20064 ((INSTANCE) == TIM5) || \
20065 ((INSTANCE) == TIM8) || \
20066 ((INSTANCE) == TIM9) || \
20067 ((INSTANCE) == TIM10)|| \
20068 ((INSTANCE) == TIM11)|| \
20069 ((INSTANCE) == TIM12)|| \
20070 ((INSTANCE) == TIM13)|| \
20071 ((INSTANCE) == TIM14))
20072
20073/****************** TIM Instances : supporting commutation event generation ***/
20074#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20075 ((INSTANCE) == TIM8))
20076
20077
20078/****************** TIM Instances : supporting OCxREF clear *******************/
20079#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20080 ((INSTANCE) == TIM2) || \
20081 ((INSTANCE) == TIM3) || \
20082 ((INSTANCE) == TIM4) || \
20083 ((INSTANCE) == TIM5) || \
20084 ((INSTANCE) == TIM8))
20085
20086/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20087#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20088 ((INSTANCE) == TIM2) || \
20089 ((INSTANCE) == TIM3) || \
20090 ((INSTANCE) == TIM4) || \
20091 ((INSTANCE) == TIM5) || \
20092 ((INSTANCE) == TIM8) || \
20093 ((INSTANCE) == TIM9) || \
20094 ((INSTANCE) == TIM12))
20095
20096/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20097#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20098 ((INSTANCE) == TIM2) || \
20099 ((INSTANCE) == TIM3) || \
20100 ((INSTANCE) == TIM4) || \
20101 ((INSTANCE) == TIM5) || \
20102 ((INSTANCE) == TIM8))
20103
20104/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
20105#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20106 ((INSTANCE) == TIM2) || \
20107 ((INSTANCE) == TIM3) || \
20108 ((INSTANCE) == TIM4) || \
20109 ((INSTANCE) == TIM5) || \
20110 ((INSTANCE) == TIM8) || \
20111 ((INSTANCE) == TIM9) || \
20112 ((INSTANCE) == TIM12))
20113
20114/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
20115#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20116 ((INSTANCE) == TIM2) || \
20117 ((INSTANCE) == TIM3) || \
20118 ((INSTANCE) == TIM4) || \
20119 ((INSTANCE) == TIM5) || \
20120 ((INSTANCE) == TIM8) || \
20121 ((INSTANCE) == TIM9) || \
20122 ((INSTANCE) == TIM12))
20123
20124/****************** TIM Instances : supporting repetition counter *************/
20125#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20126 ((INSTANCE) == TIM8))
20127
20128/****************** TIM Instances : supporting encoder interface **************/
20129#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20130 ((INSTANCE) == TIM2) || \
20131 ((INSTANCE) == TIM3) || \
20132 ((INSTANCE) == TIM4) || \
20133 ((INSTANCE) == TIM5) || \
20134 ((INSTANCE) == TIM8) || \
20135 ((INSTANCE) == TIM9) || \
20136 ((INSTANCE) == TIM12))
20137/****************** TIM Instances : supporting Hall sensor interface **********/
20138#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20139 ((INSTANCE) == TIM2) || \
20140 ((INSTANCE) == TIM3) || \
20141 ((INSTANCE) == TIM4) || \
20142 ((INSTANCE) == TIM5) || \
20143 ((INSTANCE) == TIM8))
20144/****************** TIM Instances : supporting the break function *************/
20145#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20146 ((INSTANCE) == TIM8))
20147
20148/******************** USART Instances : Synchronous mode **********************/
20149#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20150 ((INSTANCE) == USART2) || \
20151 ((INSTANCE) == USART3) || \
20152 ((INSTANCE) == USART6))
20153
20154/******************** UART Instances : Half-Duplex mode **********************/
20155#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20156 ((INSTANCE) == USART2) || \
20157 ((INSTANCE) == USART3) || \
20158 ((INSTANCE) == UART4) || \
20159 ((INSTANCE) == UART5) || \
20160 ((INSTANCE) == USART6) || \
20161 ((INSTANCE) == UART7) || \
20162 ((INSTANCE) == UART8))
20163
20164/* Legacy defines */
20165#define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20166
20167/****************** UART Instances : Hardware Flow control ********************/
20168#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20169 ((INSTANCE) == USART2) || \
20170 ((INSTANCE) == USART3) || \
20171 ((INSTANCE) == USART6))
20172/******************** UART Instances : LIN mode **********************/
20173#define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20174
20175/********************* UART Instances : Smart card mode ***********************/
20176#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20177 ((INSTANCE) == USART2) || \
20178 ((INSTANCE) == USART3) || \
20179 ((INSTANCE) == USART6))
20180
20181/*********************** UART Instances : IRDA mode ***************************/
20182#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20183 ((INSTANCE) == USART2) || \
20184 ((INSTANCE) == USART3) || \
20185 ((INSTANCE) == UART4) || \
20186 ((INSTANCE) == UART5) || \
20187 ((INSTANCE) == USART6) || \
20188 ((INSTANCE) == UART7) || \
20189 ((INSTANCE) == UART8))
20190
20191/*********************** PCD Instances ****************************************/
20192#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20193 ((INSTANCE) == USB_OTG_HS))
20194
20195/*********************** HCD Instances ****************************************/
20196#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20197 ((INSTANCE) == USB_OTG_HS))
20198
20199/****************************** SDIO Instances ********************************/
20200#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20201
20202/****************************** IWDG Instances ********************************/
20203#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20204
20205/****************************** WWDG Instances ********************************/
20206#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20207
20208
20209/****************************** QSPI Instances ********************************/
20210#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20211/****************************** USB Exported Constants ************************/
20212#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
20213#define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
20214#define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
20215#define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
20216#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
20217#define USB_OTG_HS_MAX_IN_ENDPOINTS 9U /* Including EP0 */
20218#define USB_OTG_HS_MAX_OUT_ENDPOINTS 9U /* Including EP0 */
20219#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
20220
20221/*
20222 * @brief Specific devices reset values definitions
20224#define RCC_PLLCFGR_RST_VALUE 0x24003010U
20225#define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
20226#define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
20228#define RCC_MAX_FREQUENCY 180000000U
20229#define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
20230#define RCC_MAX_FREQUENCY_SCALE2 168000000U
20231#define RCC_MAX_FREQUENCY_SCALE3 120000000U
20232#define RCC_PLLVCO_OUTPUT_MIN 192000000U
20233#define RCC_PLLVCO_INPUT_MIN 950000U
20234#define RCC_PLLVCO_INPUT_MAX 2100000U
20235#define RCC_PLLVCO_OUTPUT_MAX 432000000U
20237#define RCC_PLLN_MIN_VALUE 50U
20238#define RCC_PLLN_MAX_VALUE 432U
20240#define FLASH_SCALE1_LATENCY1_FREQ 30000000U
20241#define FLASH_SCALE1_LATENCY2_FREQ 60000000U
20242#define FLASH_SCALE1_LATENCY3_FREQ 90000000U
20243#define FLASH_SCALE1_LATENCY4_FREQ 120000000U
20244#define FLASH_SCALE1_LATENCY5_FREQ 150000000U
20246#define FLASH_SCALE2_LATENCY1_FREQ 30000000U
20247#define FLASH_SCALE2_LATENCY2_FREQ 60000000U
20248#define FLASH_SCALE2_LATENCY3_FREQ 90000000U
20249#define FLASH_SCALE2_LATENCY4_FREQ 120000000U
20250#define FLASH_SCALE2_LATENCY5_FREQ 150000000U
20252#define FLASH_SCALE3_LATENCY1_FREQ 30000000U
20253#define FLASH_SCALE3_LATENCY2_FREQ 60000000U
20254#define FLASH_SCALE3_LATENCY3_FREQ 90000000U
20255
20256/******************************************************************************/
20257/* For a painless codes migration between the STM32F4xx device product */
20258/* lines, the aliases defined below are put in place to overcome the */
20259/* differences in the interrupt handlers and IRQn definitions. */
20260/* No need to update developed interrupt code when moving across */
20261/* product lines within the same STM32F4 Family */
20262/******************************************************************************/
20263/* Aliases for __IRQn */
20264#define FSMC_IRQn FMC_IRQn
20265
20266/* Aliases for __IRQHandler */
20267#define FSMC_IRQHandler FMC_IRQHandler
20268
20272
20276
20280
20281#ifdef __cplusplus
20282}
20283#endif /* __cplusplus */
20284
20285#endif /* __STM32F469xx_H */
#define __IO
#define RESERVED(N, T)
Definition core_ca.h:179
#define FMC_IRQn
#define HASH_RNG_IRQn
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition stm32f401xc.h:66
@ PendSV_IRQn
Definition stm32f401xc.h:74
@ ETH_WKUP_IRQn
@ EXTI2_IRQn
Definition stm32f401xc.h:85
@ DMA1_Stream2_IRQn
Definition stm32f401xc.h:90
@ CAN1_SCE_IRQn
Definition stm32f405xx.h:99
@ SDIO_IRQn
@ RTC_WKUP_IRQn
Definition stm32f401xc.h:80
@ OTG_HS_EP1_IN_IRQn
@ DMA2_Stream0_IRQn
@ DMA2_Stream6_IRQn
@ UART7_IRQn
@ I2C1_ER_IRQn
@ I2C2_EV_IRQn
@ MemoryManagement_IRQn
Definition stm32f401xc.h:69
@ SAI1_IRQn
@ TIM4_IRQn
@ TIM2_IRQn
@ LTDC_ER_IRQn
@ DMA2_Stream7_IRQn
@ TIM8_BRK_TIM12_IRQn
@ USART2_IRQn
@ DMA2_Stream3_IRQn
@ SVCall_IRQn
Definition stm32f401xc.h:72
@ ADC_IRQn
Definition stm32f401xc.h:95
@ SPI3_IRQn
@ SPI2_IRQn
@ TIM7_IRQn
@ UART8_IRQn
@ CAN2_SCE_IRQn
@ RCC_IRQn
Definition stm32f401xc.h:82
@ TIM6_DAC_IRQn
@ OTG_HS_EP1_OUT_IRQn
@ I2C2_ER_IRQn
@ QUADSPI_IRQn
@ TIM8_CC_IRQn
@ UsageFault_IRQn
Definition stm32f401xc.h:71
@ SysTick_IRQn
Definition stm32f401xc.h:75
@ I2C3_ER_IRQn
@ I2C3_EV_IRQn
@ CAN2_RX0_IRQn
@ BusFault_IRQn
Definition stm32f401xc.h:70
@ SPI5_IRQn
@ DebugMonitor_IRQn
Definition stm32f401xc.h:73
@ FLASH_IRQn
Definition stm32f401xc.h:81
@ DMA2_Stream5_IRQn
@ WWDG_IRQn
Definition stm32f401xc.h:77
@ I2C1_EV_IRQn
@ TIM3_IRQn
@ DMA2_Stream1_IRQn
@ CAN1_TX_IRQn
Definition stm32f405xx.h:96
@ OTG_HS_WKUP_IRQn
@ DMA1_Stream0_IRQn
Definition stm32f401xc.h:88
@ EXTI15_10_IRQn
@ SPI4_IRQn
@ TIM1_UP_TIM10_IRQn
Definition stm32f401xc.h:98
@ EXTI9_5_IRQn
Definition stm32f401xc.h:96
@ DMA1_Stream1_IRQn
Definition stm32f401xc.h:89
@ SPI6_IRQn
@ OTG_FS_IRQn
@ OTG_FS_WKUP_IRQn
@ FPU_IRQn
@ TIM8_UP_TIM13_IRQn
@ USART6_IRQn
@ SPI1_IRQn
@ OTG_HS_IRQn
@ PVD_IRQn
Definition stm32f401xc.h:78
@ TIM1_TRG_COM_TIM11_IRQn
Definition stm32f401xc.h:99
@ TIM1_BRK_TIM9_IRQn
Definition stm32f401xc.h:97
@ CAN2_RX1_IRQn
@ EXTI0_IRQn
Definition stm32f401xc.h:83
@ CAN1_RX0_IRQn
Definition stm32f405xx.h:97
@ EXTI4_IRQn
Definition stm32f401xc.h:87
@ DSI_IRQn
@ DMA2_Stream2_IRQn
@ TAMP_STAMP_IRQn
Definition stm32f401xc.h:79
@ UART5_IRQn
@ DMA1_Stream5_IRQn
Definition stm32f401xc.h:93
@ DMA2D_IRQn
@ DCMI_IRQn
@ ETH_IRQn
@ USART1_IRQn
@ EXTI3_IRQn
Definition stm32f401xc.h:86
@ NonMaskableInt_IRQn
Definition stm32f401xc.h:68
@ UART4_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
@ EXTI1_IRQn
Definition stm32f401xc.h:84
@ DMA2_Stream4_IRQn
@ TIM5_IRQn
@ DMA1_Stream7_IRQn
@ DMA1_Stream4_IRQn
Definition stm32f401xc.h:92
@ DMA1_Stream6_IRQn
Definition stm32f401xc.h:94
@ TIM1_CC_IRQn
@ LTDC_IRQn
@ CAN2_TX_IRQn
@ CAN1_RX1_IRQn
Definition stm32f405xx.h:98
@ DMA1_Stream3_IRQn
Definition stm32f401xc.h:91
@ USART3_IRQn
@ RTC_Alarm_IRQn
Analog to Digital Converter.
Controller Area Network FIFOMailBox.
Controller Area Network FilterRegister.
Controller Area Network TxMailBox.
Controller Area Network.
CRC calculation unit.
Digital to Analog Converter.
Debug MCU.
DMA2D Controller.
DMA Controller.
DSI Controller.
__IO uint32_t FIR[2]
__IO uint32_t LPMCCR
uint32_t RESERVED2[3]
__IO uint32_t VVSACR
__IO uint32_t TDCCR
__IO uint32_t VHBPCCR
__IO uint32_t VVFPCCR
__IO uint32_t IER[2]
__IO uint32_t VMCR
__IO uint32_t VLCCR
__IO uint32_t VLCR
__IO uint32_t MCR
__IO uint32_t VVFPCR
__IO uint32_t CMCR
__IO uint32_t WCFGR
__IO uint32_t PCONFR
__IO uint32_t PTTCR
uint32_t RESERVED1[2]
__IO uint32_t VVACCR
__IO uint32_t VCCCR
__IO uint32_t LCCR
__IO uint32_t VNPCCR
__IO uint32_t WCR
uint32_t RESERVED8[155]
uint32_t RESERVED0[4]
__IO uint32_t LVCIDR
__IO uint32_t WISR
__IO uint32_t PCTLR
__IO uint32_t CCR
__IO uint32_t WRPCR
__IO uint32_t PCR
__IO uint32_t VR
__IO uint32_t PUCR
__IO uint32_t VHSACCR
__IO uint32_t VCCR
__IO uint32_t GVCIDR
__IO uint32_t WIFCR
uint32_t RESERVED10
__IO uint32_t VSCR
__IO uint32_t VHSACR
uint32_t RESERVED3[8]
__IO uint32_t GPDR
__IO uint32_t CLCR
__IO uint32_t PSR
__IO uint32_t ISR[2]
uint32_t RESERVED6[7]
__IO uint32_t VVBPCCR
__IO uint32_t GHCR
__IO uint32_t VVACR
__IO uint32_t LPCR
__IO uint32_t CR
__IO uint32_t VPCCR
uint32_t RESERVED4[2]
__IO uint32_t LCCCR
__IO uint32_t DLTCR
__IO uint32_t VPCR
__IO uint32_t WIER
uint32_t RESERVED7[11]
__IO uint32_t VNPCR
__IO uint32_t TDCR
__IO uint32_t VMCCR
__IO uint32_t GPSR
uint32_t RESERVED9
__IO uint32_t LPMCR
uint32_t RESERVED5
__IO uint32_t VVBPCR
__IO uint32_t LCVCIDR
__IO uint32_t LCOLCR
__IO uint32_t CLTCR
__IO uint32_t VVSACCR
__IO uint32_t WPCR[5]
__IO uint32_t TCCR[6]
__IO uint32_t VHBPCR
Ethernet MAC.
External Interrupt/Event Controller.
FLASH Registers.
Flexible Memory Controller.
Flexible Memory Controller Bank1E.
Flexible Memory Controller Bank3.
Flexible Memory Controller Bank5_6.
General Purpose I/O.
Inter-integrated Circuit Interface.
Independent WATCHDOG.
LCD-TFT Display layer x Controller.
LCD-TFT Display Controller.
Power Control.
QUAD Serial Peripheral Interface.
Reset and Clock Control.
Real-Time Clock.
Serial Audio Interface.
SD host Interface.
Serial Peripheral Interface.
System configuration controller.
Universal Synchronous Asynchronous Receiver Transmitter.
USB_OTG_device_Registers.
USB_OTG_Core_Registers.
USB_OTG_Host_Channel_Specific_Registers.
USB_OTG_Host_Mode_Register_Structures.
USB_OTG_IN_Endpoint-Specific_Register.
USB_OTG_OUT_Endpoint-Specific_Registers.
Window WATCHDOG.
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.